# US 10,770,382 B2 · Low inductance stackable solid-state switching module and method of manufacturing thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,382 B2 - Document ID: US10770382B2 - Status: Granted - Kind: B2 - Application number: 16/203,777 - Filed: 2018-11-29 - Published: 2020-06-04 - Granted: 2020-09-08 - Earliest claimed: 2018-11-29 - Assignees: General Electric Company - Applicants: General Electric Company - Inventors: Christopher James Kapusta; Ramanujam Ramabhadran; Kum-Kang Huh; Brian Lynn Rowden; Glenn Scott Claydon; Ahmed Elasser - Web page: https://patentgrep.com/patent/US10770382B2 ## CPC - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 74/114: {by a substrate and the encapsulations} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/01: Manufacture or treatment - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H02M 3/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections} - H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes} - H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A modular electronics package is disclosed that includes a first and second electronics packages, with each of the first and second electronics packages including a metallized insulating substrate and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate. A conductive joining material is positioned between the first electronics package and the second electronics package to electrically connect them together. The first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions. ## Claims ### Claim 1 A modular electronics package comprising: a pair of electronics packages comprising a first electronics package and a second electronics package, each of the first and second electronics packages comprising: a metallized insulating substrate comprising an insulating layer and a first conductor layer positioned on the insulating layer; and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate; and a conductive joining material positioned between the first electronics package and the second electronics package to electrically connect the first electronics package to the second electronics package; wherein the first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions. ### Claim 2 (depends on 1) The electronics package of claim 1 wherein the current path and the return current path through the solid-state switching devices in the first and second electronics packages provide cancellation of fields generated during switching of the solid-state switching devices, so as to reduce a commutation loop inductance in the half-bridge unit cell. ### Claim 3 (depends on 1) The electronics package of claim 1 wherein the commutation loop inductance in the half-bridge unit cell is 0.5 nH or less. ### Claim 4 (depends on 1) The electronics package of claim 1 wherein the metallized insulating substrate of at least one of the first electronics package and the second electronics package comprises a plurality of conductive vias formed through the insulating layer, the plurality of conductive through-vias electrically coupled to the first conductor layer and in direct contact with the plurality of contact pads. ### Claim 5 (depends on 4) The electronics package of claim 4 wherein at least one of the first electronics package and the second electronics package further comprises a component attach material coupling the solid-state switching device to the metallized insulating substrate, and wherein the plurality of conductive vias is formed through the insulating layer and the component attach material to be in direct contact with the plurality of contact pads. ### Claim 6 (depends on 1) The electronics package of claim 1 wherein the metallized insulating substrate of at least one of the first electronics package and the second electronics package further comprises a second conductor layer positioned on the insulating layer on a side thereof opposite first conductor layer, and wherein the solid-state switching device is joined to the first metal layer of the metallized insulating substrate via a flip-chip attachment. ### Claim 7 (depends on 1) The electronics package of claim 1 wherein at least one of the first electronics package and the second electronics package further comprises at least one additional electrical component positioned on the metallized insulating substrate, and at least one additional electrical component including one or more of a gate driver, a resistor, and a capacitor. ### Claim 8 (depends on 7) The electronics package of claim 7 wherein the at least one of the first electronics package and the second electronics package further comprises an encapsulant that surrounds the solid-state switching device and the at least one additional electrical component. ### Claim 9 (depends on 1) The electronics package of claim 1 wherein the first electronics package and the second electronics package are stacked in a back-to-back arrangement, such that the metallized insulating substrates of the electronics packages are adjacent one another. ### Claim 10 (depends on 9) The electronics package of claim 9 further comprising an insulating spacer positioned between the metallized insulating substrates of the first and second electronics packages, with the conductive joining material positioned at locations between the first and second electronics packages left exposed by the insulating spacer. ### Claim 11 (depends on 9) The electronics package of claim 9 wherein the metallized insulating substrate of each of the first and second electronics packages includes a plurality of through-vias formed therein, with the through-vias of the first electronics package and the through-vias of the second electronics package being aligned with one another. ### Claim 12 (depends on 11) The electronics package of claim 11 further comprising conductive through-vias positioned in the plurality of through-vias to electrically connect the first electronics package to the second electronics package, the conductive through-vias comprising one of a solder fill or a solder fill and pin. ### Claim 13 (depends on 1) The electronics package of claim 1 wherein the first electronics package and the second electronics package are stacked in a front-to-front arrangement, such that the solid-state switching devices of the first and second electronics packages are positioned between the metallized insulating substrates of the electronics packages, with the solid-state switching devices being adjacent one another in a side-by-side arrangement. ### Claim 14 (depends on 1) The electronics package of claim 1 wherein the metallized insulating substrate comprises drain and source connections thereon, and wherein the drain and source connections of the first electronics package and the drain and source connections of the second electronics package are offset from one another when stacked with one another to form the half-bridge unit cell. ### Claim 15 (depends on 1) The electronics package of claim 1 further comprising an additional pair of electronics packages comprising a third electronics package and a fourth electronics package that are stacked with one another to form another half-bridge unit cell, with the half-bridge unit cell formed by the third and fourth electronics packages operatively connected with the half-bridge unit cell formed by the first and second electronics packages to form a full-bridge circuit or a pair of parallel connected half-bridge unit cells. ### Claim 16 (depends on 15) The electronics package of claim 15 wherein the half-bridge unit cell formed by the first and second electronics packages is stacked with the half-bridge unit cell formed by the third and fourth electronics packages, with a thermal interface material positioned between the half-bridge unit cells. ### Claim 17 A method of manufacturing a half-bridge unit cell comprising: providing a first electronics package and a second electronics package of identical construction, each of the first and second electronics packages comprising: a metallized insulating substrate comprising an insulating layer and a metal layer positioned on the insulating layer; and a solid-state switching device positioned on the metallized insulating substrate and electrically coupled thereto; forming a plurality of through-vias in the metallized insulating substrate of each of the first and second electronics packages that extend through the metallized insulating substrate; vertically stacking the first electronics package with the second electronics package, with the plurality of through-vias in the metallized insulating substrate of the first electronics package being aligned with the plurality of through-vias in the metallized insulating substrate of the second electronics package; and physically and electrically coupling the first electronics package with the second electronics package to form a commutation loop in the half-bridge unit cell. ### Claim 18 (depends on 17) The method of claim 17 wherein physically and electrically coupling the first electronics package with the second electronics package comprises applying a conductive joining material between the first electronics package and the second electronics package. ### Claim 19 (depends on 18) The method of claim 18 wherein applying the conductive joining material comprises forming conductive through-vias positioned in the plurality of through-vias. ### Claim 20 (depends on 17) The method of claim 17 wherein providing each of the first electronics package and the second electronics package comprises: applying a component attach material to the insulating layer; coupling the solid-state switching device to the insulating layer via the component attach material; forming a plurality of conductive vias formed through the insulating layer and the component attach material and down to contact pads on the solid-state switching device, the plurality of conductive through-vias electrically coupled to the metal layer. ### Claim 21 (depends on 17) The method of claim 17 wherein providing each of the first electronics package and the second electronics package comprises physically and electrically coupling the solid-state switching device to the metal layer of the metallized insulating substrate via a flip-chip attachment. ### Claim 22 (depends on 17) The method of claim 17 wherein vertically stacking the first electronics package with the second electronics package comprises vertically stacking the first electronics package and the second electronics package in a back-to-back arrangement, such that the metallized insulating substrates of the electronics packages are adjacent one another; and wherein the method further comprises positioning an insulating spacer between the metallized insulating substrates of the first and second electronics packages. ### Claim 23 (depends on 17) The method of claim 17 wherein vertically stacking the first electronics package with the second electronics package comprises vertically stacking the first electronics package and the second electronics package in front-to-front arrangement, such that the solid-state switching devices of the first and second electronics packages are positioned between the metallized insulating substrates of the electronics packages, with the solid-state switching devices being adjacent one another in a side-by-side arrangement. ### Claim 24 A half-bridge unit cell comprising: a first electronics package comprising a first wide-bandgap semiconductor switch coupled to a first metallized insulating substrate, the first wide-bandgap semiconductor switch electrically connected to a conductor layer of the first metallized insulating substrate; and a second electronics package comprising a second wide-bandgap semiconductor switch coupled to a second metallized insulating substrate, the second wide-bandgap semiconductor switch electrically connected to a conductor layer of the second metallized insulating substrate; wherein the first electronics package is stacked vertically with the second electronics package and electrically coupled thereto to form a commutation loop in the half-bridge unit cell, with an inductance of the commutation loop in the half-bridge unit cell being 0.5 nH or less. ### Claim 25 (depends on 24) The half-bridge unit cell of claim 24 wherein the first electronics package and the second electronics package are stacked in one of a back-to-back arrangement and a front-to-front arrangement, with the first and second metallized insulating substrates adjacent one another and the first and second wide-bandgap semiconductor switches opposite one another when in the back-to-back arrangement, and with the first and second wide-bandgap semiconductor switches positioned adjacent one another in a side-by-side arrangement between the first and second metallized insulating substrates when in the front-to-front arrangement. ### Claim 26 (depends on 24) The half-bridge unit cell of claim 24 wherein each of the first electronics package and the second electronics package comprises drain and source connections thereon, and wherein the drain and source connections of the first electronics package and the drain and source connections of the second electronics package are offset from one another when stacked vertically with one another. ### Claim 27 (depends on 24) The half-bridge unit cell of claim 24 wherein each of the first metallized insulating substrate and the second metallized insulating substrate comprises: an insulating layer having a plurality of vias formed therein; and a conductor layer positioned on the insulating layer and in the plurality of via, such that the conductor layer includes a plurality of conductive vias formed through the insulating layer; wherein the plurality of conductive vias are in direct contact with contact pads of a respective one of the first wide-bandgap semiconductor switch and the second wide-bandgap semiconductor switch.