# US 10,770,375 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,375 B2 - Document ID: US10770375B2 - Status: Granted - Kind: B2 - Application number: 16/247,054 - Filed: 2019-01-14 - Published: 2019-08-22 - Granted: 2020-09-08 - Earliest claimed: 2018-02-19 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Jun Shibata - Web page: https://patentgrep.com/patent/US10770375B2 ## CPC - H10W 70/411: {Chip-supporting parts, e.g. die pads} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 70/421: {Shapes or dispositions} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/457: {of metallic layers on leadframes} - H10W 72/0198: {batch processes} - H10W 72/90: Bond pads, in general - H10W 74/014: {using batch processing} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 74/473: {containing a filler} - H10W 70/461: {specially adapted for cooling} - H10W 70/465: {Bumps or wires} - H10W 72/073: {of die-attach connectors} - H10W 72/07336: {Soldering or alloying} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/075: {of bond wires} - H10W 72/07532: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device according to one embodiment of the present invention includes a wire electrically connecting a die pad and a semiconductor chip mounted on the die pad to each other, and an encapsulation body encapsulating the semiconductor chip. The die pad includes a wire-bonding region to which the wire is connected and a through hole penetrating through the die pad in a thickness direction. The wire-bonding region is covered by a metal film partially covering the die pad. The through hole is formed at a position overlapping the metal film. The encapsulation body includes a first portion formed over the die pad, a second portion formed under the die pad, and a third portion buried in the through hole of the die pad, wherein the first portion and the second portion of the encapsulation body are connected with each other via the third portion. ## Claims ### Claim 1 A semiconductor device comprising: a die pad including a first main surface and a second main surface opposite to the first main surface; a semiconductor chip mounted on the first main surface of the die pad, the semiconductor chip including a first front surface, a first rear surface opposite to the first front surface, and a plurality of electrodes arranged on the first front surface; a plurality of leads including a first lead facing the die pad in plan view, the plurality of leads being arranged at positions so as to be spaced apart from the die pad, the plurality of leads being electrically connected with the semiconductor chip; a plurality of wires including a first wire and a second wire; and an encapsulation body encapsulating the semiconductor chip, the plurality of wires, and the die pad, wherein the plurality of electrodes of the semiconductor chip includes 1) a first electrode electrically connected with the first lead via the first wire, and 2) a second electrode electrically connected with the die pad via the second wire, wherein the die pad includes 1) a wire-bonding region that is A) not overlapping with the semiconductor chip in plan view and B) covered by a first metal film partially covering the first main surface of the die pad, and 2) a first through hole that penetrates through the die pad from the first main surface to the second main surface, wherein the second wire is bonded to the first metal film in the wire-bonding region, wherein the first through hole is formed at a position overlapping with the first metal film or around the first metal film, and wherein an opening area of the first through hole is smaller than an area of the first metal film in plan view. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the encapsulation body includes: a first portion formed over the first main surface of the die pad, a second portion formed under the second main surface of the die pad, and a third portion buried in the first through hole of the die pad, and wherein the first portion and the second portion of the encapsulation body are connected with each other via the third portion. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the first through hole is formed at a position overlapping the first metal film in plan view. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein an entire first through hole completely overlaps the first metal film in plan view. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein a plurality of the first through holes are formed in or in a periphery of the wire-bonding region, and wherein at least one or more of the plurality of first through holes is formed at a position overlapping the first metal film in plan view. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein some of the plurality of first through holes are arranged along a peripheral portion of the first metal film in plan view. ### Claim 7 (depends on 2) The semiconductor device according to claim 2, wherein a peripheral portion of the die pad includes a first side facing the plurality of leads, wherein the wire-bonding region includes a first wire-bonding region and a second wire-bonding region, wherein the first wire-bonding region and the second wire-bonding region are arranged along the first side, wherein the first metal film in the first wire-bonding region and the first metal film in the second wire-bonding region are spaced apart from each other, in plan view, without intervening any metal film therebetween, and wherein the first through hole is formed at the position overlapping with the first metal film covering the wire-bonding region including the first wire-bonding region and the second wire-bonding region. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein a width of the first metal film in the first wire-bonding region in a first direction is smaller than a separation distance between the first metal film in the first wire-bonding region and the first metal film in the second wire-bonding region in the first direction, the first direction extending along an extending direction of the first side. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein each of the plurality of leads facing the first side of the die pad includes a tip portion covered by a second metal film made of the same metal material as the first metal film, and wherein a width of the first metal film in the first wire-bonding region is larger than a width of the tip portion of each of the plurality of leads in the first direction. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein a plurality of the first through holes is formed in the first wire-bonding region, and wherein an opening area of each of the plurality of first through holes in the first wire-bonding region is smaller than a planar area of the first metal film. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein each of the plurality of leads facing the first side of the die pad includes a tip portion covered by a second metal film made of the same metal material as the first metal film, and wherein an opening width of each of the plurality of first through holes is larger than a width of the tip portion of each of the plurality of leads in the first direction. ### Claim 12 (depends on 2) The semiconductor device according to claim 2, wherein a plurality of the first through holes is formed in the wire-bonding region, and wherein an opening area of each of the plurality of first through holes is smaller than a planar area of the first metal film. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the die pad comprises a plurality of second through holes overlapping a die-bonding region overlapping the semiconductor chip in plan view and penetrating through the die pad from the first main surface to the second main surface, wherein a portion of the first rear surface of the semiconductor chip is adhered to the encapsulation body, and wherein an opening area of each of the plurality of first through holes is smaller than an opening area of each of the plurality of second through holes. ### Claim 14 (depends on 2) The semiconductor device according to claim 2, wherein an inner wall of the first through hole is covered by the first metal film. ### Claim 15 (depends on 2) The semiconductor device according to claim 2, wherein an adhesive strength between the first metal film and the encapsulation body is lower than an adhesive strength between a substrate of the die pad and the encapsulation body. ### Claim 16 (depends on 2) The semiconductor device according to claim 2, wherein a plurality of suspension leads extending from a peripheral portion of the die pad to a peripheral portion of the encapsulation body is connected with the die pad, wherein the wire-bonding region exists at a plurality of regions of the die pad, wherein the plurality of regions is spaced apart from each other, and wherein the plurality of regions includes: a first wire-bonding region formed over an extended line of any of the plurality of suspension leads, and a second wire-bonding region formed at a position that differs from the extended line of any of the plurality of suspension leads. ### Claim 17 (depends on 2) The semiconductor device according to claim 2, wherein the encapsulation body includes resin and a plurality of filler particles that are mixed in the resin, and wherein an opening width of the first through hole is larger than a particle size of each of the plurality of filler particles. ### Claim 18 A semiconductor device comprising: a die pad including 1) a first side extending in a first direction, 2) a first main surface, and 3) a second main surface opposite to the first main surface; a semiconductor chip mounted on the first main surface of the die pad, the semiconductor chip including 1) a first front surface, 2) a first rear surface opposite to the first front surface, and 3) a plurality of electrodes arranged on the first front surface; a plurality of leads including a first lead facing the die pad in plan view, arranged at positions so as to be spaced apart from the die pad, and electrically connected with the semiconductor chip; a plurality of wires including a first wire and a second wire; and an encapsulation body encapsulating the semiconductor chip, the plurality of wires and the die pad, wherein the plurality of electrodes of the semiconductor chip includes a first electrode electrically connected with the first lead via a first wire, and a second electrode electrically connected with the die pad via a second wire, wherein the die pad includes a wire-bonding region that is not overlapping the semiconductor chip in plan view, and that is covered by a first metal film partially covering the first main surface of the die pad, a first through hole and penetrating through the die pad from the first main surface to the second main surface, and a second through hole penetrating through the die pad from the first main surface to the second main surface, wherein the second wire is bonded to the first metal film in the wire-bonding region which is surrounded with the first through hole, the second through hole and the first side of the die pad, wherein each of the first and second through holes is formed at a position overlapping with the first metal film or around the first metal film, and wherein an opening area of each of the first and second through holes is smaller than an area of the first metal film in plan view. ### Claim 19 (depends on 18) The semiconductor device according to claim 18, wherein, in plan view, the first and second through holes are formed between the first side of the die pad and the semiconductor chip, and wherein the first and second through holes are arranged along the first side extending in the first direction. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the first and second through holes are closer to the first side of the die pad than the semiconductor chip is to the first side of the die pad, in plan view.