# US 10,770,367 B2 · Semiconductor apparatus, method for manufacturing the same and electric power conversion device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,367 B2 - Document ID: US10770367B2 - Status: Granted - Kind: B2 - Application number: 16/159,745 - Filed: 2018-10-15 - Published: 2019-10-03 - Granted: 2020-09-08 - Earliest claimed: 2018-03-30 - Assignees: Mitsubishi Electric Corporation - Applicants: Mitsubishi Electric Corporation - Inventors: Takuya Kitabayashi; Hiroshi Yoshida; Hidetoshi Ishibashi; Daisuke Murata - Web page: https://patentgrep.com/patent/US10770367B2 ## CPC - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 76/10: Containers or parts thereof - H10W 76/157: having interconnections parallel to the insulating or insulated base - H10W 76/60: Seals - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 72/073: {of die-attach connectors} - H10W 72/07331: {Connecting techniques} - H10W 72/07336: {Soldering or alloying} - H10W 72/075: {of bond wires} - H10W 72/07532: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 76/47: Solid or gel fillings - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor apparatus includes: a substrate including a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a side face of the substrate. ## Claims ### Claim 1 A semiconductor apparatus comprising: a substrate including an insulator disposed between a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate, a gap being between the case and a lateral side face of the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on the lateral side face of the substrate, the bonding agent extending along a bottom surface of the case and filling the gap between the case and the lateral side face of the substrate. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein a lower part of the case includes a protrusion that makes contact with an upper surface of the metal plate. ### Claim 3 (depends on 1) The semiconductor apparatus according to claim 1, wherein a lower part of the case includes a step. ### Claim 4 (depends on 2) The semiconductor apparatus according to claim 2, wherein a lower part of the case includes a step. ### Claim 5 (depends on 1) The semiconductor apparatus according to claim 1, wherein the bonding agent covers a lower part of the case that is higher than the bottom surface of the case. ### Claim 6 (depends on 2) The semiconductor apparatus according to claim 2, wherein the bonding agent covers the protrusion. ### Claim 7 (depends on 3) The semiconductor apparatus according to claim 3, wherein the bonding agent covers the step. ### Claim 8 (depends on 4) The semiconductor apparatus according to claim 4, wherein the bonding agent covers one or both of the protrusion and the step. ### Claim 9 (depends on 1) An electric power conversion device comprising: a main conversion circuit including the semiconductor apparatus according to claim 1, converting input power and outputting converted power; and a control circuit outputting a control signal for controlling the main conversion circuit to the main conversion circuit. ### Claim 10 (depends on 1) The semiconductor apparatus of claim 1, wherein the bonding agent includes a thermoplastic resin. ### Claim 11 A semiconductor apparatus comprising: a substrate including an insulator disposed between a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a lateral side face of the substrate, the bonding agent covering a bottom surface of the case. ### Claim 12 (depends on 11) The semiconductor apparatus according to claim 11, wherein a bottom surface of the bonding agent is coplanar with a bottom surface of the metal plate. ### Claim 13 A semiconductor apparatus comprising: a substrate including an insulator disposed between a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent covering a lower inner part, a lower outer part, and a lower surface of the case, bonding the lower inner part of the case and a lateral side face of the metal plate on a lateral side face of the substrate.