# US 10,770,366 B2 · Integrated circuit packages and methods for forming the same

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- Number: US 10,770,366 B2
- Document ID: US10770366B2
- Status: Granted
- Kind: B2
- Application number: 16/694,349
- Filed: 2019-11-25
- Published: 2020-03-19
- Granted: 2020-09-08
- Earliest claimed: 2012-06-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chia-Wei Tu; Hsien-Wei Chen; Tsung-Fu Tsai; Wen-Hsiung Lu; Yian-Liang Kuo
- Web page: https://patentgrep.com/patent/US10770366B2

## CPC

- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/656: Fan-in layouts
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

## Claims

### Claim 1

A method comprising:
forming a solder region on a wafer, wherein the wafer comprises a plurality of chips, with the solder region being in a first chip of the plurality of chips;
forming a dielectric layer to embed a portion of the solder region in the dielectric layer, wherein the dielectric layer comprises a first portion and a second portion;
thinning the first portion of the dielectric layer without thinning the second portion of the dielectric layer; and
sawing the wafer to separate the plurality of chips from each other, wherein the sawing comprises using a feature underlying the thinned first portion of the dielectric layer for alignment.

### Claim 2 (depends on 1)

The method of claim 1, wherein the thinning results in a trench to be formed in the dielectric layer, wherein the trench extends into the first chip.

### Claim 3 (depends on 2)

The method of claim 2, wherein the trench further extends into a scribe line, with the scribe line separating the first chip and a second chip from each other.

### Claim 4 (depends on 1)

The method of claim 1, wherein after the thinning, a remaining portion of the first portion of the dielectric layer is left, and has a thickness allowing the feature directly underlying the remaining portion to be visible through the remaining portion.

### Claim 5 (depends on 1)

The method of claim 1, wherein before the thinning, the first portion of the dielectric layer is thick enough to prevent the feature from being visible through the first portion of the dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the dielectric layer comprises a molding compound.

### Claim 7 (depends on 1)

The method of claim 1, wherein the thinning is performed using a blade.

### Claim 8 (depends on 1)

The method of claim 1, wherein the thinned first portion of the dielectric layer has a first thickness in a range between about 1 percent and about 40 percent of a second thickness of the second portion of the dielectric layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the feature used for aligning comprises a seal ring in the first chip.

### Claim 10

A method comprising:
forming a first electrical connector and a second electrical connector on a first chip and a second chip of a wafer;
molding the first electrical connector and the second electrical connector to be partially in a molding compound;
performing a first sawing process to form a trench in the molding compound, wherein the trench comprises a first portion extending into the first chip, wherein after the first sawing process, a conductive feature is visible through a remaining portion of the molding compound directly underlying the trench; and
after the first sawing process, performing a second sawing process to saw through a scribe line that separates the first chip and the second chip from each other, wherein in the second sawing process, the conductive feature is used as an alignment mark.

### Claim 11 (depends on 10)

The method of claim 10, wherein the trench further extends into the scribe line, and a kerf of the second sawing process passes through the scribe line.

### Claim 12 (depends on 11)

The method of claim 11, wherein the trench further extends into the second chip.

### Claim 13 (depends on 10)

The method of claim 10, wherein the conductive feature comprises a seal ring.

### Claim 14 (depends on 10)

The method of claim 10, wherein sidewalls of the trench are tilted, and wherein a bottom of the trench is substantially flat.

### Claim 15 (depends on 10)

The method of claim 10, wherein the first sawing process is performed using a blade.

### Claim 16 (depends on 10)

The method of claim 10, wherein before the first sawing process, the conductive feature is not visible through the molding compound.

### Claim 17 (depends on 10)

The method of claim 10, wherein after the second sawing process, a notch ring is generated in a peripheral region of the first chip.

### Claim 18

A method comprising:
molding a wafer comprising a first chip and a second chip with a molding compound, wherein a solder region in the first chip is partially molded in the molding compound;
performing a thinning process to thin the molding compound, until a feature underlying the molding compound is visible; and
after the thinning process, performing a die-saw process to separate the first chip and the second chip from each other, wherein the feature is used as an alignment mark.

### Claim 19 (depends on 18)

The method of claim 18, wherein when the feature is used as the alignment mark, a remaining portion of the molding compound remains directly over the alignment mark, and the feature is viewed through the remaining portion of the molding compound.

### Claim 20 (depends on 18)

The method of claim 18, wherein before the thinning process, the feature is not visible through the molding compound.