# US 10,770,364 B2 · Chip scale package (CSP) including shim die > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,364 B2 - Document ID: US10770364B2 - Status: Granted - Kind: B2 - Application number: 15/951,941 - Filed: 2018-04-12 - Published: 2019-10-17 - Granted: 2020-09-08 - Earliest claimed: 2018-04-12 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Hong Shi; Suresh Ramalingam; Siow Chek Tan; Gamal Refai-Ahmed - Web page: https://patentgrep.com/patent/US10770364B2 ## CPC - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H10W 40/10: Arrangements for heating - H10W 72/07254: {changes in dispositions} - H10W 72/07354: {changes in dispositions} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/874: {On different surfaces} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/9413: {on encapsulations} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/20: Configurations of stacked chips - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die. ## Claims ### Claim 1 A structure comprising: a first integrated circuit die; a shim die being a dummy die having no active or passive circuitry thereon; an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die; a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant, wherein the redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die, conductive bumps attached to the redistribution structure, the conductive bumps including a plurality of input/output (IO) bumps aligned in a direction and contained within a dimension, the dimension being a sum of: (i) a dimension of the first integrated circuit die along the direction, (ii) a dimension of the shim die along the direction, (iii) a dimension of the encapsulant disposed along the direction and between a side opposite from the first integrated circuit die and another side opposite from the shim die. ### Claim 2 (depends on 1) The structure of claim 1 further comprising a heat sink attached to the first integrated circuit die and the shim die, the heat sink being opposite from the redistribution structure. ### Claim 3 (depends on 1) The structure of claim 1, wherein at least some of the IO bumps are on an area of the redistribution structure aligned with and parallel to an area of the shim die. ### Claim 4 (depends on 3) The structure of claim 3 further comprising a package substrate attached to the conductive bumps. ### Claim 5 (depends on 1) The structure of claim 1, wherein the first integrated circuit die includes input/output (IO) connector components on an active side of the first integrated circuit die, the IO connector components being in one or more columns, each of the one or more columns having, in a layout of the first integrated circuit die, a first region of the first integrated circuit die and a second region of the first integrated circuit die on opposing sides of the respective column. ### Claim 6 (depends on 5) The structure of claim 5, wherein the IO bumps are connected to the IO connector components through the one or more metal layers of the redistribution structure, wherein at least some of the IO are on an area of the redistribution structure aligned with and parallel to an area of the shim die. ### Claim 7 (depends on 5) The structure of claim 5 wherein: the IO bumps are connected to the IO connector components through routing of the one or more metal layers of the redistribution structure; at least some of the routing extends in the redistribution structure in a region defined by lateral boundaries of the shim die; and a pitch of the IO bumps is greater than a pitch of the IO connector components. ### Claim 8 (depends on 5) The structure of claim 5, wherein the first region and the second region are respective logic regions of the first integrated circuit die. ### Claim 9 (depends on 5) The structure of claim 5 further comprising a second integrated circuit die stacked on a backside of the first integrated circuit die, the second integrated circuit die comprising logic integrated circuitry. ### Claim 10 (depends on 1) The structure of claim 1, wherein the first integrated circuit die includes input/output (IO) connector components on an active side of the first integrated circuit die, the IO connector components being along a periphery region of the first integrated circuit die. ### Claim 11 (depends on 10) The structure of claim 10, wherein the IO bumps are connected to the IO connector components through the one or more metal layers of the redistribution structure, wherein at least some of the IO bumps are on an area of the redistribution structure aligned with and parallel to an area of the shim die. ### Claim 12 (depends on 10) The structure of claim 10, wherein: the IO bumps are connected to the IO connector components through routing of the one or more metal layers of the redistribution structure; at least some of the routing extends in the redistribution structure in a region defined by lateral boundaries of the shim die; and a pitch of the IO bumps is greater than a pitch of the IO connector components. ### Claim 13 A structure, comprising: a first integrated circuit die; a shim die; an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die; a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant, wherein the redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die; a number of input/output (IO) bumps aligned in a direction is equal to a dimension divided by a linear pitch of the IO bumps along the direction; and the dimension is a sum of: (i) a dimension of the first integrated circuit die along the direction, (ii) a dimension of the shim die along the direction, (iii) a dimension of the encapsulant disposed along the direction and between the shim die and the first integrated circuit die, (iv) a dimension of the encapsulant extending along the direction and from the shim die on a side opposite from the first integrated circuit die, and (v) a dimension of the encapsulant extending along the direction and from the first integrated circuit die on a side opposite from the shim die. ### Claim 14 A structure comprising: a chip scale package (CSP) comprising: an integrated circuit die; a shim die being a dummy die having no active or passive circuitry thereon; an encapsulant at least laterally encapsulating the integrated circuit die and the shim die; a redistribution structure on the integrated circuit die, the shim die, and the encapsulant, the redistribution structure including one or more metal layers electrically connected to the integrated circuit die, conductive bumps attached to the redistribution structure and electrically connected to the one or more metal layers, the conductive bumps including a plurality of input/output (IO) bumps aligned in a direction and contained within a dimension, the dimension being a sum of: (i) a dimension of the integrated circuit die along the direction, (ii) a dimension of the shim die along the direction, (iii) a dimension of the encapsulant disposed along the direction and between a side opposite from the integrated circuit die and another side opposite from the shim die; a package substrate attached to the conductive bumps. ### Claim 15 (depends on 14) The structure of claim 14 further comprising a heat sink attached to the CSP opposite from the conductive bumps. ### Claim 16 (depends on 14) The structure of claim 14, wherein the shim die includes an integrated passive device electrically connected to the one or more metal layers. ### Claim 17 (depends on 14) The structure of claim 14, wherein at least some of the conductive bumps are disposed in a region, the region being between the shim die and the package substrate in a direction perpendicular to a surface of the package substrate to which the conductive bumps are attached. ### Claim 18 (depends on 14) The structure of claim 14, wherein the CSP further comprises a stack of dies, the encapsulant further at least laterally encapsulating the stack of dies. ### Claim 19 (depends on 13) The structure of claim 13, wherein the shim die includes an integrated passive device electrically connected to the one or more metal layers. ### Claim 20 (depends on 13) The structure of claim 13, further comprising a heat sink attached to the first integrated circuit die and the shim die, the heat sink being opposite from the redistribution structure.