# US 10,770,360 B2 · Semiconductor structures and fabrication methods thereof

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- Number: US 10,770,360 B2
- Document ID: US10770360B2
- Status: Granted
- Kind: B2
- Application number: 15/496,026
- Filed: 2017-04-25
- Published: 2018-01-11
- Granted: 2020-09-08
- Earliest claimed: 2016-07-07
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Fei Zhou
- Web page: https://patentgrep.com/patent/US10770360B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening.

## Claims

### Claim 1

A method for fabricating a semiconductor structure, comprising:
providing a base structure having a first transistor region and a second transistor region, wherein the base structure includes a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in the first transistor region, and a plurality of second openings formed in the dielectric layer in the second transistor region;
forming a first work function layer on the dielectric layer and covering bottom and sidewall surfaces of each of the plurality of the first opening and of each of the plurality of the second opening;
forming a first sacrificial layer in each first opening and each second opening, wherein a top surface of the first sacrificial layer is lower than a top surface of the dielectric layer;
removing a portion of the first work function layer exposed by the first sacrificial layer in each first opening and each second opening using the first sacrificial layer as a first etch mask;
forming a second sacrificial layer in the second transistor region;
removing the first sacrificial layer from each first opening after removing the portion of the first work function layer formed in each first opening and a remaining portion of the first work function layer formed in each first opening by etching using the second sacrificial layer as a second etch mask;
removing the second sacrificial layer in the second transistor region;
removing the first sacrificial layer from each second opening after removing the remaining portion of the first work function layer formed in each first opening, wherein the second sacrificial layer and the first sacrificial layer are removed by a same etching process after removing the portion of the first work function layer formed in the first transistor region; and
forming a second work function layer and then a gate electrode in each first opening and each second opening.

### Claim 2 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein removing the first sacrificial layer from each first opening and removing the first sacrificial layer from each second opening include ashing, dry etching, or wet etching.

### Claim 3 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1,
wherein forming the first sacrificial layer includes:
forming a first initial sacrificial layer on the first work function layer; and
forming the first sacrificial layer by removing a portion of the first initial sacrificial layer formed in each first opening and each second opening as well as the first initial sacrificial layer formed on the dielectric layer.

### Claim 4 (depends on 3)

The method for fabricating the semiconductor structure according to claim 3, wherein forming the first initial sacrificial layer includes a spin-coating or slot-die coating process.

### Claim 5 (depends on 3)

The method for fabricating the semiconductor structure according to claim 3, wherein removing the portion of the first initial sacrificial layer formed in each first opening and each second opening as well as the first initial sacrificial layer formed on the dielectric layer includes one or more of a wet etching process and a dry etching process.

### Claim 6 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein removing the remaining portion of the first work function layer formed in each first opening includes:
forming a second initial sacrificial layer on the dielectric layer and directly on the first sacrificial layer in each first opening and each second opening;
forming a patterned photoresist layer on the second initial sacrificial layer, wherein the patterned photoresist layer exposes a portion of the second initial sacrificial layer formed in the first transistor region;
forming the second sacrificial layer in the second transistor region by removing the portion of the second initial sacrificial layer formed in the first transistor region using the patterned photoresist layer as an etch mask; and
removing the patterned photoresist layer after removing the portion of the first work function layer formed in the first transistor region.

### Claim 7 (depends on 6)

The method for fabricating the semiconductor structure according to claim 6, wherein the first sacrificial layer and the second sacrificial layer are made of a same material.

### Claim 8 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein the first sacrificial layer is an organic anti-reflection coating layer.

### Claim 9 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, further including:
forming N-type metal-oxide-semiconductor (NMOS) transistors in the first transistor region;
forming P-type metal-oxide-semiconductor (PMOS) transistors in the second transistor region;
the first work function layer is made of TiNx or TiON; and
the second work function layer is made of titanium aluminide.

### Claim 10 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, further including:
forming PMOS transistors in the first transistor region;
forming NMOS transistors in the second transistor region;
the first work function layer is made of titanium aluminide; and
the second work function layer is made of TiNx or TiON.

### Claim 11 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, further including:
a covering layer, sandwiched by the second work function layer and the gate electrode, on the second work function layer, wherein the second work function layer is formed on the substrate in the first opening and the second work function layer is formed directly on and completely covers the first work function layer in the second opening.

### Claim 12 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein after removing the portion of the first work function layer exposed by the first sacrificial layer in each first opening and each second opening using the first sacrificial layer:
the top surface of the dielectric layer is completely exposed, and the sidewall surfaces of each of the plurality of the first opening and of each of the plurality of the second opening are partially exposed.