# US 10,770,358 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,770,358 B2
- Document ID: US10770358B2
- Status: Granted
- Kind: B2
- Application number: 16/201,694
- Filed: 2018-11-27
- Published: 2019-05-02
- Granted: 2020-09-08
- Earliest claimed: 2017-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Mark Van Dal; Gerben Doornbos
- Web page: https://patentgrep.com/patent/US10770358B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor wire structure horizontally extending over a substrate and having a channel region, and a source region and a drain region disposed at ends of the channel region in a horizontal direction, wherein:
a source contact layer is formed over the source region,
the source contact layer is embedded in an dielectric layer,
an isolation insulating layer is disposed between the dielectric layer and the substrate,
a bottom of the source region is separated from the substrate by an insulating layer made of a different material than the isolation insulating layer and the dielectric layer, and a bottom of the drain region is separated from the substrate by the insulating layer,
the substrate includes a protrusion below the source region, and
the insulating layer is disposed between the bottom of the source region and the protrusion.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the insulating layer is made of SiCO.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the dielectric layer is made of silicon oxide.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, the source region of the semiconductor wire structure and the protrusion are made of a same material.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate structure including a gate dielectric layer and a metal gate electrode layer,
wherein the gate dielectric layer wraps around the channel region of the semiconductor wire structure.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a silicide layer is disposed between the source region and the source contact layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a bottom of the source contact layer is separated from the isolation insulating layer by the insulating layer.

### Claim 8

A semiconductor device, comprising:
a first semiconductor wire structure horizontally extending and having a channel region, and a source region and a drain region, which are disposed at ends of the channel region in a horizontal direction; and
a second semiconductor wire structure horizontally extending and having a channel region, and a source region and a drain region, which are disposed at ends of the channel region in a horizontal direction, wherein:
a source contact layer is formed over the source region of the first semiconductor wire structure and the source region of the second semiconductor wire structure,
the source contact layer is embedded in a dielectric layer,
an isolation insulating layer is disposed between the dielectric layer and a substrate,
a bottom of the source region of the first semiconductor wire structure and a bottom of the source region of the second semiconductor wire structure are separated from the substrate by an insulating layer made of a different material than the isolation insulating layer and the dielectric layer,
a bottom of the drain region of the first semiconductor wire structure and a bottom of the drain region of the second semiconductor wire structure are separated from the substrate by the insulating layer,
the substrate includes a first protrusion below the source region of the first semiconductor wire structure and a second protrusion below the source region of the second semiconductor wire structure, and
the insulating layer is disposed between the bottom of the source region of the first semiconductor wire structure and the first protrusion and between the bottom of the source region of the second semiconductor wire structure and the second protrusion.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the insulating layer is made of SiCO.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein:
the substrate includes a first protrusion below the source region of the first semiconductor wire structure and a second protrusion below the source region of the second semiconductor wire structure, and
the insulating layer is disposed between the bottom of the source region of the first semiconductor wire structure and the first protrusion and between the bottom of the source region of the second semiconductor wire structure and the second protrusion.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, the first and second semiconductor wire structures and the substrate are made of a same material.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, the first and second semiconductor wire structures and the substrate are made of different materials.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein:
a first silicide layer is disposed between the source region of the first semiconductor wire structure and the source contact layer, and
a second silicide layer is disposed between the source region of the second semiconductor wire structure and the source contact layer.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein a bottom of the source contact layer is separated from the isolation insulating layer by the insulating layer.

### Claim 15

A semiconductor device, comprising:
semiconductor wire structures horizontally extending over a substrate, each of which have a channel region, and a source region and a drain region, which are disposed at ends of the channel region in a horizontal direction, wherein:
a source contact layer is formed over the source region wrapping around the semiconductor wires,
the source contact layer is embedded in an dielectric layer,
an isolation insulating layer is disposed between the dielectric layer and the substrate,
a bottom of the source region is separated from the substrate by an insulating layer made of a different material than the isolation insulating layer and the dielectric layer, and a bottom of the drain region is separated from the substrate by the insulating layer,
the substrate includes a protrusion below the source region, and
the insulating layer is disposed between the bottom of the source/drain region and the protrusion.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the insulating layer is made of SiCO.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the protrusion continuously extends from the substrate and is made of a same material as the substrate.

### Claim 18 (depends on 8)

The semiconductor device of claim 8, wherein the isolation insulating layer is made of silicon oxide.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein a bottom of the source contact layer is separated from the isolation insulating layer by the insulating layer.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the dielectric layer is made of silicon oxide.