# US 10,770,354 B2 · Method of forming integrated circuit with low-k sidewall spacers for gate stacks

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- Number: US 10,770,354 B2
- Document ID: US10770354B2
- Status: Granted
- Kind: B2
- Application number: 15/813,742
- Filed: 2017-11-15
- Published: 2019-05-16
- Granted: 2020-09-08
- Earliest claimed: 2017-11-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yen-Ting Chen; Wei-Yang Lee; Feng-Cheng Yang; Yen-Ming Chen
- Web page: https://patentgrep.com/patent/US10770354B2

## CPC

- H10D 64/679: {comprising air gaps}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

## Claims

### Claim 1

A method comprising:
receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate;
forming a spacer on a side surface of the gate stack;
curing the spacer to form a cured spacer having a plurality of voids from the curing, wherein the cured spacer includes a spacer layer with a low-k dielectric material, the low-k dielectric material is a material having a dielectric constant of 1 to less than 3.9, wherein the low-k dielectric material includes a dielectric material and a dopant selected from the group consisting of an n-type dopant and a p-type dopant;
forming a source/drain region in the substrate; and
forming a source/drain contact coupled to the source/drain region, wherein the spacer layer of the cured spacer is disposed between the source/drain contact and the gate stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein the low-k dielectric material includes a porous low-k dielectric material.

### Claim 3 (depends on 2)

The method of claim 2, wherein the forming of the spacer includes depositing a low-k dielectric material precursor and a porogen; and
wherein the curing of the spacer to from the cured spacer includes curing the low-k dielectric material precursor to form the low-k dielectric material of the spacer layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the received gate stack includes a placeholder gate electrode; and
the curing of the low-k dielectric material precursor is performed after removing the placeholder gate electrode and before forming a functional gate electrode of the gate stack.

### Claim 5 (depends on 3)

The method of claim 3, wherein the curing of the low-k dielectric material precursor includes applying ultra-violet radiation to the workpiece.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming of the spacer includes:
depositing the dielectric material on the gate stack; and
in situ implanting the dopant during the depositing of the dielectric material.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming of the spacer includes:
depositing the dielectric material on the gate stack; and
thereafter performing an ion implantation process upon the workpiece to implant the dopant within the dielectric material.

### Claim 8 (depends on 1)

The method of claim 1, wherein the curing of the spacer to form the cured spacer includes heating the workpiece to a temperature between 350° C. and 450° C., and
wherein the curing occurs in an environment selected from the group consisting of an inert-gas environment and a vacuum environment.

### Claim 9 (depends on 1)

The method of claim 1, wherein the curing of the spacer includes exposing the spacer to radiation having one or more wavelengths between 150 nm and 250 nm for between 50 and 150 seconds.

### Claim 10

A method comprising:
receiving a substrate and a gate stack disposed on the substrate;
forming a sidewall spacer on a vertical side surface of the gate stack, wherein the sidewall spacer includes a low-k dielectric precursor, wherein the low-k dielectric precursor includes a dielectric material selected from the group consisting of a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and a semiconductor oxycarbonitride;
curing the sidewall spacer to form a cured sidewall spacer, wherein the curing of the sidewall spacer includes curing the low-k dielectric precursor to form a low-k dielectric material of the cured sidewall spacer, wherein the curing forms a void within the low-k dielectric material, wherein the low-k dielectric material is a material having a dielectric constant of 1 to less than 3.9;
forming a source/drain contact adjacent the gate stack such that the cured sidewall spacer is disposed between the source/drain contact and the gate stack;
removing a placeholder gate electrode from the gate stack; and
forming a functional gate electrode of the gate stack, and
wherein the curing of the low-k dielectric precursor is performed after the removing of the placeholder gate electrode and prior to the forming of the functional gate electrode.

### Claim 11 (depends on 10)

The method of claim 10, wherein the sidewall spacer further includes a porogen, and
wherein the curing of the low-k dielectric precursor causes the porogen of the sidewall spacer to form the void within the low-k dielectric material, and the porogen remains within the cured sidewall spacer after the curing.

### Claim 12 (depends on 10)

The method of claim 10, further comprising forming a contact etch-stop layer directly on the sidewall spacer.

### Claim 13 (depends on 12)

The method of claim 12, wherein after the curing of the sidewall spacer to form the cured sidewall spacer, the contact etch-stop layer physically contacts the cured sidewall spacer, and
wherein after the forming of the source/drain contact, the contact etch-stop layer physically contacts the source/drain contact.

### Claim 14

A method comprising:
forming a gate stack over a substrate;
forming a sidewall spacer on the gate stack;
curing the sidewall spacer to form a cured sidewall spacer having a plurality of voids from the curing, wherein the cured sidewall spacer is formed of a low-k dielectric material, wherein the low-k dielectric material is a material having a dielectric constant of 1 to less than 3.9, wherein the low-k dielectric material includes a dielectric material and a dopant selected from the group consisting of an n-type dopant and a p-type dopant; and
after curing the sidewall spacer, forming a source/drain contact adjacent the gate stack such that the cured sidewall spacer is disposed between the source/drain contact and the gate stack.

### Claim 15 (depends on 14)

The method of claim 14, wherein the sidewall spacer is formed of a low-k dielectric material precursor and a porogen,
wherein the low-k dielectric material precursor includes a material selected from the group consisting of tetraethylorthosilicate (TEOS), tetramethoxysilane (TMOS), methyltrimethoxysilane (MTMS), methyltriethoxysilane (MTES), and diethoxy methyl silane (DEMS), and
wherein the porogen is selected from the group consisting of α-Terpinene (ATRP) and polystyrene.

### Claim 16 (depends on 14)

The method of claim 14, wherein the sidewall spacer includes a low-k precursor material having a dopant selected from the group consisting of B, BF2, P and As, and
wherein the low-k precursor material has a concentration of the dopant between 1×1016 atoms/cm3 and 1×1021 atoms/cm3.

### Claim 17 (depends on 14)

The method of claim 14, further comprising performing a dopant activation process to activate the dopant, and
wherein the substrate is part of a workpiece,
wherein the dopant activation process includes heating the workpiece to a temperature between 450° C. and 1050° C., and
wherein the dopant activation process occurs either prior to the curing of the sidewall spacer to form the cured sidewall spacer or during the curing of the sidewall spacer to form the cured sidewall spacer.

### Claim 18 (depends on 14)

The method of claim 14, wherein the sidewall spacer includes a low-k dielectric precursor, and
wherein the curing of the sidewall spacer includes curing the low-k dielectric precursor to form the low-k dielectric material of the cured sidewall spacer, and
wherein the low-k dielectric precursor includes a dielectric material selected from the group consisting of a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and a semiconductor oxycarbonitride.

### Claim 19 (depends on 14)

The method of claim 14, wherein the dopant is selected from the group consisting of B, BF2, P and As.

### Claim 20 (depends on 14)

The method of claim 14, further comprising removing a first gate electrode from the gate stack, and
wherein the curing of the sidewall spacer to form the cured sidewall spacer occurs after the removing of the first gate electrode, and
wherein the forming of the second gate electrode of the gate stack occurs after the curing of the sidewall spacer.