# US 10,770,352 B2 · Semiconductor device and fabrication method thereof

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- Number: US 10,770,352 B2
- Document ID: US10770352B2
- Status: Granted
- Kind: B2
- Application number: 15/834,681
- Filed: 2017-12-07
- Published: 2018-06-14
- Granted: 2020-09-08
- Earliest claimed: 2016-12-08
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Fei Zhou
- Web page: https://patentgrep.com/patent/US10770352B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- C23F 1/00: Etching metallic material by chemical means (manufacture of printing surfaces B41C; manufacture of printed circuits H05K)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/834: {comprising FinFETs}
- H10P 50/266: {by vapour etching only}
- H10P 50/268: {of silicon-containing layers}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8325: {Silicon carbide}
- H10D 84/0158: {the components including FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- C23F: NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE (working metal by laser beams B23K26/00; desurfacing by applying flames B23K7/00; working of metal by electro-erosion B23H; producing decorative effects by removing surface material, e.g. by engraving, by etching, B44C1/22; electrolytic etching or polishing C25F); INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a first region for forming a first transistor and a second region for forming a second transistor, the first transistor having a working current less than the second transistor. The fabrication method further includes forming a gate electrode layer on the base substrate; etching the gate electrode layer to form a first gate electrode in the first region; after forming the first gate electrode, etching the gate electrode layer to form a second gate electrode in the second region, with the second gate electrode having an undercut structure; forming a first source/drain doped region in the base substrate on both sides of the first gate electrode and forming a second source/drain region in the base substrate on both sides of the second gate electrode.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
providing a base substrate including a first region for forming a first transistor and a second region for forming a second transistor, the first transistor having a working current less than the second transistor;
forming a gate electrode layer on the base substrate;
etching the gate electrode layer to form a first gate electrode in the first region;
after forming the first gate electrode, etching the gate electrode layer to form a second gate electrode in the second region, with the second gate electrode having an undercut structure, wherein the undercut structure has a stepped sidewall including a first step portion on the base substrate and a second step portion on the first step portion, wherein the first step portion has a smaller size than the second step portion in a direction parallel to a surface of the base substrate; and
forming a first source/drain doped region in the base substrate on both sides of the first gate electrode and forming a second source/drain doped region in the base substrate on both sides of the second gate electrode wherein: the base substrate includes a substrate and a plurality of fins on the substrate; the first gate electrode is formed across the fin in the first region, covering a portion of a top and sidewall of the fin in the first region; the first gate electrode is formed across the fin in the first region, covering a portion of a top and sidewall of the fin in the first region; the second gate electrode is formed across the fin in the second region, covering a portion of a top and sidewall of the fin in the second region; the first source/drain doped region is formed within the fin in the first region on both sides of the first gate electrode; and the second source/drain doped region is formed within the fin in the second region on both sides of the second gate electrode.

### Claim 2 (depends on 1)

The method of forming a semiconductor device according to claim 1, wherein:
the first gate electrode has a footing structure.

### Claim 3 (depends on 1)

The method of forming a semiconductor device according to claim 1, wherein forming the second gate electrode comprises:
forming a photoresist layer on the first gate electrode and on the gate electrode layer in the second region; and
etching the gate electrode layer using the photoresist layer as an etching mask to form the second gate electrode.

### Claim 4 (depends on 1)

The method of forming a semiconductor device according to claim 1, wherein etching the gate electrode layer to form the first gate electrode in the first region comprises:
forming a hard mask layer on the gate electrode layer of the first region; and
etching the gate electrode layer using the hard mask layer as an etching mask to form the first gate electrode.

### Claim 5 (depends on 1)

The method of forming a semiconductor device according to claim 1, wherein:
the first transistor formed in the first region includes a core device; and
the second transistor formed in the second region includes an TO device.

### Claim 6 (depends on 2)

The method of forming a semiconductor device according to claim 2, wherein:
the footing structure has a stepped sidewall including a third step portion on the base substrate and a fourth step portion on the third step portion; and
the third step portion has a larger size than the fourth step portion in a direction parallel to a surface of the base substrate.

### Claim 7 (depends on 1)

The method of forming a semiconductor device according to claim 1, wherein etching process parameters for forming the second gate electrode comprise:
an etching gas including a mixed gas of HBr, He and O2,
a gas flow rate of HBr being approximately 50˜1000 sccm,
a gas flow rate of He being approximately 300˜1500 sccm,
a gas flow rate of 02 being approximately 1˜20 sccm,
a pressure of approximately 30˜250 mtorr,
an etching time of approximately 10˜200 s, and
a RF power of approximately 700˜3000 W.

### Claim 8 (depends on 1)

The method of forming a semiconductor device according to claim 1, wherein etching process parameters for forming the first gate electrode comprise:
an etching gas including a mixed gas of CF4, SF6, N2 and O2,
a gas flow rate of CF4 being approximately 50˜175 sccm,
a gas flow rate of SF6 being approximately 5˜81 sccm,
a gas flow rate of N2 being approximately 6˜75 sccm,
a gas flow rate of O2 being approximately 1˜25 sccm,
a pressure of approximately 1˜150 mtorr,
an etching time of approximately 10˜2000 s,
a voltage of approximately 50˜300 V, and
a RF power of approximately 200˜500 W.

### Claim 9 (depends on 1)

The method of forming a semiconductor device according to claim 1, wherein forming the first source/drain doped region comprises:
etching a portion of the base substrate on both sides of the first gate electrode to form a first trench in the base substrate on both sides of the first gate electrode; and
forming a source/drain epitaxial doped layer filling the first trench, the source/drain epitaxial doped layer being doped with P-type ions or N-type ions.

### Claim 10 (depends on 1)

The method of forming a semiconductor device according to claim 1, wherein forming the second source/drain doped region comprises:
etching a portion of the base substrate on both sides of the second gate electrode to form a second trench in the base substrate on both sides of the second gate electrode; and
forming a source/drain epitaxial doped layer filling the second trench, the source/drain epitaxial doped layer being doped with P-type ions or N-type ions.

### Claim 11

A method of forming a semiconductor device, comprising:
providing a base substrate including a first region for forming a first transistor and a second region for forming a second transistor, the first transistor having a working current less than the second transistor;
forming a gate electrode layer on the base substrate;
etching the gate electrode layer to form a first gate electrode in the first region;
after forming the first gate electrode, etching the gate electrode layer to form a second gate electrode in the second region, with the second gate electrode having an undercut structure;
forming a first source/drain doped region in the base substrate on both sides of the first gate electrode and forming a second source/drain doped region in the base substrate on both sides of the second gate electrode;
forming an interlayer dielectric layer on portions of the base substrate exposed by the first gate electrode and the second gate electrode;
removing the first gate electrode and the second gate electrode to respectively form a first opening and a second opening in the interlayer dielectric layer; and
filling the first opening and the second opening with a metal to form a first metal gate electrode and a second metal gate electrode.

### Claim 12 (depends on 11)

The method of forming a semiconductor device according to claim 11, wherein:
the base substrate includes a substrate and a plurality of fins on the substrate;
the first gate electrode is formed across the fin in the first region, covering a portion of a top and sidewall of the fin in the first region;
the second gate electrode is formed across the fin in the second region, covering a portion of a top and sidewall of the fin in the second region;
the first source/drain doped region is formed within the fin in the first region on both sides of the first gate electrode; and
the second source/drain doped region is formed within the fin in the second region on both sides of the second gate electrode.

### Claim 13 (depends on 11)

The method of forming a semiconductor device according to claim 11, wherein:
the first gate electrode has a footing structure.

### Claim 14 (depends on 11)

The method of forming a semiconductor device according to claim 11, wherein forming the second gate electrode comprises:
forming a photoresist layer on the first gate electrode and on the gate electrode layer in the second region; and
etching the gate electrode layer using the photoresist layer as an etching mask to form the second gate electrode.

### Claim 15 (depends on 11)

The method of forming a semiconductor device according to claim 11, wherein etching the gate electrode layer to form the first gate electrode in the first region comprises:
forming a hard mask layer on the gate electrode layer of the first region; and
etching the gate electrode layer using the hard mask layer as an etching mask to form the first gate electrode.

### Claim 16 (depends on 11)

The method of forming a semiconductor device according to claim 11, wherein:
the first transistor formed in the first region includes a core device; and
the second transistor formed in the second region includes an TO device.

### Claim 17 (depends on 11)

The method of forming a semiconductor device according to claim 11, wherein:
the undercut structure has a stepped sidewall including a first step portion on the base substrate and a second step portion on the first step portion; and
the first step portion has a smaller size than the second step portion in a direction parallel to a surface of the base substrate.

### Claim 18 (depends on 13)

The method of forming a semiconductor device according to claim 13, wherein:
the footing structure has a stepped sidewall including a third step portion on the base substrate and a fourth step portion on the third step portion; and
the third step portion has a larger size than the fourth step portion in a direction parallel to a surface of the base substrate.