# US 10,770,333 B2 · Wafer level flat no-lead semiconductor packages and methods of manufacture

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- Number: US 10,770,333 B2
- Document ID: US10770333B2
- Status: Granted
- Kind: B2
- Application number: 16/293,168
- Filed: 2019-03-05
- Published: 2019-06-27
- Granted: 2020-09-08
- Earliest claimed: 2014-07-25
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Darrell D. Truhitte; James P. Letterman, Jr.
- Web page: https://patentgrep.com/patent/US10770333B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 70/042: {Etching}
- H10W 72/0198: {batch processes}
- H10W 74/014: {using batch processing}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7438: {with parts of the auxiliary support remaining in the finished device}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 40/10: Arrangements for heating
- H10W 70/442: {of multiple leadframes in a single chip}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/013: {of die-attach connectors}
- H10W 72/01304: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01325: {in solid form}
- H10W 72/01333: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01335: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01351: {Changing the shapes of die-attach connectors}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/07178: {Means for aligning}
- H10W 72/072: {of bump connectors}
- H10W 72/07234: {Using a reflow oven}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07334: {Using a reflow oven}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/07354: {changes in dispositions}
- H10W 72/075: {of bond wires}
- H10W 72/07507: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07554: {changes in dispositions}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

## Claims

### Claim 1

A method of manufacturing a semiconductor package, the method comprising:
providing a substrate, the substrate having a first side, a second side, and a thickness where the first side of the substrate comprises a pattern;
bonding a wafer comprising a plurality of semiconductor die to the first side of the substrate at one or more die pads comprised in each one of the plurality of semiconductor die;
one of overmolding or underfilling the first side of the substrate with one of an overmold material or an underfill material, respectively;
from the second side of the substrate, selectively removing one or more portions of the thickness of the substrate; and
singulating the plurality of semiconductor die and one of the overmold material or the underfill material to form a plurality of semiconductor packages.

### Claim 2 (depends on 1)

The method of claim 1, wherein providing the substrate further comprises wherein the pattern comprised in the first side of the substrate is formed by a process selected from the group consisting of selectively etching the pattern into the first side of the substrate, stamping the pattern into the first side of the substrate, selectively plating the pattern onto the first side of the substrate, and any combination thereof.

### Claim 3 (depends on 1)

The method of claim 1, further comprising stacking two or more of the plurality of semiconductor packages and one of electrically coupling and mechanically coupling the two or more stacked semiconductor packages thereby.

### Claim 4 (depends on 1)

The method of claim 1, further comprising coupling a heat dissipation device to each of the plurality of semiconductor packages, the heat dissipation device being placed in contact with the plurality of semiconductor die.

### Claim 5 (depends on 1)

The method of claim 1, wherein singulating the plurality of semiconductor die and one of the overmold material or the underfill material to form the plurality of semiconductor packages further comprises selectively singulating leaving two or more of the plurality of semiconductor packages coupled together where the coupling of the two or more semiconductor packages is one of electrical or mechanical.

### Claim 6 (depends on 1)

The method of claim 1, wherein each semiconductor die of the plurality of semiconductor die is coupled over two die pads.

### Claim 7 (depends on 1)

The method of claim 1, wherein a metal layer separates the one or more die pads and the wafer.

### Claim 8

A method of manufacturing a semiconductor package, the method comprising:
patterning a first side of a substrate;
coupling a wafer comprising a plurality of semiconductor die to the first side of the substrate;
applying a mold compound to the first side of the substrate;
exposing the mold compound by selectively removing one or more portions of the second side of the substrate; and
singulating the plurality of semiconductor die and mold compound to form a plurality of semiconductor packages.

### Claim 9 (depends on 8)

The method of claim 8, wherein patterning the substrate comprises forming a plurality of cavities in the first side of the substrate between a central portion of the substrate and two die pads of the substrate.

### Claim 10 (depends on 8)

The method of claim 8, further comprising coupling a first metal plate to the first side of the substrate and coupling a second metal plate to the second side of the substrate.

### Claim 11 (depends on 8)

The method of claim 8, wherein the wafer is directly coupled to a central portion of the substrate and a metal plate is coupled between a die pad of the substrate and the wafer.

### Claim 12 (depends on 8)

The method of claim 8, wherein selectively removing one or more portions of the second side of the substrate comprises etching the second side of the substrate.

### Claim 13 (depends on 8)

The method of claim 8, wherein each semiconductor die of the plurality of semiconductor die covers a central portion of the substrate and two die pads of the substrate.

### Claim 14 (depends on 8)

The method of claim 8, wherein a thickness of a die pad formed in the substrate is less than a thickness of a central portion of the substrate.

### Claim 15

A method of manufacturing a semiconductor package, the method comprising:
forming one or more recesses in a first side of a substrate, wherein the one or more recesses separate one or more die pads of the substrate from a central portion of the substrate;
coupling a wafer comprising a plurality of semiconductor die to the first side of the substrate;
removing one or more portions of the substrate between the central portion of the substrate and the one or more die pads of the substrate; and
singulating the plurality of semiconductor die.

### Claim 16 (depends on 15)

The method of claim 15, further comprising coupling a first metal plate to a first side of the substrate and coupling a second metal plate to a second side of the substrate.

### Claim 17 (depends on 15)

The method of claim 15, wherein the wafer is directly coupled to the central portion of the substrate and a metal plate is coupled between the one or more die pads of the substrate and the wafer.

### Claim 18 (depends on 15)

The method of claim 15, wherein removing one or more portions of the substrate comprises etching the substrate from the second side of the substrate.

### Claim 19 (depends on 15)

The method of claim 15, further comprising applying a mold compound within the one or more recesses.

### Claim 20 (depends on 19)

The method of claim 19, wherein the mold compound comprises an epoxy resin.