# US 10,770,311 B2 · Stack package and methods of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,311 B2 - Document ID: US10770311B2 - Status: Granted - Kind: B2 - Application number: 16/135,114 - Filed: 2018-09-19 - Published: 2019-03-21 - Granted: 2020-09-08 - Earliest claimed: 2017-09-21 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jae-in Won; Jong-kak Jang; Dong-woo Kang; Do-yeon Kim - Web page: https://patentgrep.com/patent/US10770311B2 ## CPC - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/016: {using moulds} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/552: {comprising metals or metalloids, e.g. silver} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/555: {of outermost layers of multilayered bond wires, e.g. material of a coating} - H10W 90/721: {of bump connectors} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer. ## Claims ### Claim 1 A method of manufacturing a stack package, the method comprising: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other so that the molding resin material layer contacts an upper surface of the first semiconductor device; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer, wherein the compressing of the first package substrate and the second package substrate comprises: reflowing the molding resin material layer so that the molding resin material layer contacts side surfaces of the first semiconductor device; and electrically connecting the first package substrate and the second package substrate. ### Claim 2 (depends on 1) The method of claim 1, wherein the step of reflowing of the molding resin material layer partially and temporally overlaps with the step of electrically connecting of the first package substrate and the second package substrate. ### Claim 3 (depends on 2) The method of claim 2, wherein a starting point of the step of reflowing is temporally earlier than a starting point of the step of electrically connecting. ### Claim 4 (depends on 2) The method of claim 2, wherein a plurality of first conductive connection terminals are provided on the first surface of the first package substrate, a plurality of second conductive connection terminals are provided on the first surface of the second package substrate, each of the plurality of second conductive connection terminals respectively corresponding to each of the plurality of first conductive connection terminals, the reflowing of the molding resin material layer comprises heating the molding resin material layer up to a first temperature, and the electrical connecting of the first package substrate and the second package substrate comprises heating the plurality of first conductive connection terminals and the plurality of second conductive connection terminals up to a second temperature higher than the first temperature. ### Claim 5 (depends on 1) The method of claim 1, wherein a thickness of the molding resin material layer before being reflowed is greater than heights of the second conductive connection terminals in a vertical direction. ### Claim 6 (depends on 1) The method of claim 1, wherein the arranging of the first surface of the first package substrate and the first surface of the second package substrate to face each other comprises: fixing the first package substrate to an upper mold; and fixing the second package substrate to a lower mold, and the compressing of the first package substrate and the second package substrate comprises reducing a pressure between the first package substrate and the second package substrate. ### Claim 7 (depends on 6) The method of claim 6, wherein the compressing of the first package substrate and the second package substrate comprises: contacting the molding resin material layer to the first semiconductor device at a third temperature; and relatively moving the molding resin material layer closer to the first package substrate at a fourth temperature higher than the third temperature. ### Claim 8 (depends on 7) The method of claim 7, wherein the relatively moving of the molding resin material layer closer to the first package substrate at the fourth temperature comprises further reducing a pressure between the first package substrate and the second package substrate. ### Claim 9 (depends on 1) The method of claim 1, further comprising, filling underfill in a gap between the first package substrate and the first semiconductor device before the compressing of the first package substrate and the second package substrate. ### Claim 10 (depends on 1) The method of claim 1, further comprising, after the hardening of the molding resin material layer, trimming the molding resin material layer protruding in lateral directions of the first package substrate. ### Claim 11 A method of manufacturing a stack package, the method comprising: arranging a first surface of a first package substrate and a first surface of a second package substrate to face each other, wherein a first semiconductor device and a plurality of first conductive connection terminals are provided on the first surface of the first package substrate, and a molding resin material layer and a plurality of second conductive connection terminals corresponding to the plurality of first conductive connection terminals are provided on the first surface of the second package substrate, and the molding resin material layer contacts an upper surface of the first semiconductor device; and joining the first package substrate and the second package substrate by raising temperatures of the first package substrate and the second package substrate, wherein the joining of the first package substrate and the second package substrate by raising the temperatures of the first package substrate and the second package substrate comprises: reflowing the molding resin material layer so that the molding resin material layer contacts side surfaces of the first semiconductor device; and electrically connecting the first package substrate with the second package substrate, and wherein the step of reflowing of the molding resin material layer partially and temporally overlaps with the step of the electrically connecting of the first package substrate and the second package substrate. ### Claim 12 (depends on 11) The method of claim 11, wherein each of the first conductive connection terminals and each of the second conductive connection terminals corresponding thereto are combined to form unified and integrated connectors, wherein an upper portion and a lower portion of each connector are substantially symmetrical to each other. ### Claim 13 (depends on 12) The method of claim 12, wherein each connector has a larger horizontal cross-sectional area at a center portion, and the farther the horizontal cross-sectional area is from the center portion, the horizontal cross-sectional area decreases gradually. ### Claim 14 (depends on 12) The method of claim 12, wherein each connector is 8-shaped. ### Claim 15 (depends on 12) The method of claim 12, wherein voids do not exist between the connectors and the molding resin material layer due to the joining of the first package substrate and the second package substrate by raising the temperatures of the first package substrate and the second package substrate. ### Claim 16 (depends on 11) The method of claim 11, wherein the second package substrate is an interposer.