# US 10,770,303 B2 · Mechanisms for forming patterns using multiple lithography processes

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- Number: US 10,770,303 B2
- Document ID: US10770303B2
- Status: Granted
- Kind: B2
- Application number: 16/397,439
- Filed: 2019-04-29
- Published: 2019-08-22
- Granted: 2020-09-08
- Earliest claimed: 2014-06-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih-Ming Chang; Ming-Feng Shieh; Chih-Ming Lai; Ru-Gun Liu; Tsai-Sheng Gau
- Web page: https://patentgrep.com/patent/US10770303B2

## CPC

- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
- G03F 7/70466: {Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 50/242: {of Group IV materials}
- H10P 50/246: {of Group III-V materials}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 70/273: {the processing being a delineation of conductive layers, e.g. by RIE}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

## Claims

### Claim 1

A method for forming patterns in a semiconductor device, comprising:
forming a main pattern in a patterning-target layer over a substrate;
forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer;
patterning the hard mask layer to form a first cut pattern;
forming a second cut pattern in a first resist layer formed over the hard mask layer;
patterning the middle layer through an opening corresponding to a first intersection portion to expose a portion of the patterning-target layer, the exposed portion of the patterning-target layer corresponding to a second intersection portion;
forming a fill layer to fill the opening;
etching the middle layer using the fill layer and the hard mask layer as etching masks to expose one or more portions of the patterning-target layer; and
etching the one or more exposed portions of the patterning-target layer using the fill layer and the hard mask layer as etching masks to form a final pattern in the patterning-target layer,
wherein the first intersection portion corresponds to an intersection between the first cut pattern and the second cut pattern, and
wherein the second intersection portion corresponds to an intersection between the first intersection portion and the main pattern.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the main pattern includes:
forming a second resist layer over the patterning-target layer;
forming the main pattern in the second resist layer; and
etching the patterning-target layer using the second resist layer as an etching mask to form the main pattern in the patterning-target layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the patterning the hard mask layer to form the first cut pattern includes:
forming a third resist layer on the hard mask layer;
forming the first cut pattern in the third resist layer; and
etching the hard mask layer using the third resist layer as an etching mask to form the first cut pattern in the hard mask layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming the fill layer includes:
forming a fill layer to fill open areas in the middle layer, the hard mask layer, and the first resist layer;
removing a portion of the fill layer and a portion of the first resist layer that are disposed above the hard mask layer using a chemical mechanical polishing (CMP) process; and
removing the first resist layer filled in the first opening of the hard mask layer using an etching process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the final pattern includes:
F=M−(M∩(P1−(P1∩P2)))=M−((M∩P1)−(P1∩P2)))
where F is the final pattern, M is the main pattern, P1 is the first pattern, and P2 is the second pattern.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second cut pattern extends along a direction that is perpendicular to a direction along which the first cut pattern extends.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming the first resist layer directly over the hard mask layer such that the first layer physically contacts the hard mask layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first cut pattern and the second cut patterns include perpendicular trench features.

### Claim 9

A method for forming patterns in a semiconductor device, comprising:
providing a substrate and a patterning-target layer over the substrate;
patterning the patterning-target layer to form a main pattern;
forming a middle layer over the patterning-target layer;
forming a hard mask layer over the middle layer;
patterning the hard mask layer to form a first cut pattern;
forming a first resist layer over the hard mask layer;
patterning the first resist layer to form a second cut pattern,
patterning the middle layer through an opening corresponding to a first intersection portion to expose a portion of the patterning-target layer, the exposed portion of the patterning-target layer corresponding to a second intersection portion;
forming a fill layer to fill the opening;
etching the middle layer using the fill layer and the hard mask layer as etching masks to expose one or more portions of the patterning-target layer; and
etching the one or more exposed portions of the patterning-target layer using the fill layer and the hard mask layer as etching masks to form a final pattern in the patterning-target layer,
wherein the first intersection portion corresponds to an intersection between the first cut pattern and the second cut pattern, and
wherein the second intersection portion corresponds to an intersection between the first intersection portion and the main pattern.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming the main pattern includes:
forming a second resist layer over the patterning-target layer;
forming the main pattern in the second resist layer; and
etching the patterning-target layer using the second resist layer as an etching mask to form the main pattern in the patterning-target layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein the patterning the hard mask layer to form the first cut pattern includes:
forming a third resist layer on the hard mask layer;
forming the first cut pattern in the third resist layer; and
etching the hard mask layer using the third resist layer as an etching mask to form the first cut pattern in the hard mask layer.

### Claim 12 (depends on 10)

The method of claim 10, further comprising removing the second resist layer using one or more processes from a group consisting of a wet stripping process, a plasma ashing process, and a combination thereof.

### Claim 13 (depends on 12)

The method of claim 12, wherein the plasma ashing process includes using one or more gases selected from the group consisting of oxygen (O2), carbon dioxide (CO2), nitrogen (N2), hydrogen (H2), and a combination thereof.

### Claim 14 (depends on 11)

The method of claim 11, wherein etching the hard mask layer includes using an etching gas from the group consisting of carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), and a combination thereof.

### Claim 15 (depends on 11)

The method of claim 11, further comprising removing the hard mask layer after patterning the first portion of the middle layer.

### Claim 16

A method for forming patterns in a semiconductor device, comprising:
forming a patterning-target layer over a substrate;
forming a main pattern in the patterning-target layer;
forming a film stack over the patterning-target layer, the film stack including a middle layer, a hard mask layer, and a first resist layer;
forming a first cut pattern in the first resist layer;
forming a second cut pattern in the first resist layer;
patterning the middle layer through an opening corresponding to a first intersection portion to expose a portion of the patterning-target layer, the exposed portion of the patterning-target layer corresponding to a second intersection portion;
forming a fill layer to fill the opening;
etching the middle layer using the fill layer and the hard mask layer as etching masks to expose one or more portions of the patterning-target layer; and
etching the one or more exposed portions of the patterning-target layer using the fill layer and the hard mask layer as etching masks to form a final pattern in the patterning-target layer,
wherein the first intersection portion corresponds to an intersection between the first cut pattern and the second cut pattern, and
wherein the second intersection portion corresponds to an intersection between the first intersection portion and the main pattern.

### Claim 17 (depends on 16)

The method of claim 16, wherein the final pattern includes:
F=M−(M∩(P1−(P1∩P2)))=M−((M∩P1)−(P1∩P2)))
where F is the final pattern, M is the main pattern, P1 is the first pattern, and P2 is the second pattern.

### Claim 18 (depends on 16)

The method of claim 16, wherein the final pattern has sharp corners.

### Claim 19 (depends on 16)

The method of claim 16, further comprising transferring the second intersection pattern to the patterning-target layer by etching a portion of the patterning-target layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein after etching a portion of the patterning-target layer, a portion of the substrate is exposed.