# US 10,770,302 B2 · Semiconductor FinFET device and method

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- Number: US 10,770,302 B2
- Document ID: US10770302B2
- Status: Granted
- Kind: B2
- Application number: 16/277,023
- Filed: 2019-02-15
- Published: 2020-04-02
- Granted: 2020-09-08
- Earliest claimed: 2018-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Yu Wang
- Web page: https://patentgrep.com/patent/US10770302B2

## CPC

- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/57: the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 50/283: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes depositing a mask layer over a semiconductor substrate, etching the mask layer to form a patterned mask, wherein a sidewall of the patterned mask includes a first sidewall region, a second sidewall region, and a third sidewall region, wherein the first sidewall region is farther from the semiconductor substrate than the second sidewall region and the second sidewall region is farther from the semiconductor substrate than the third sidewall region, wherein the second sidewall region protrudes laterally from the first sidewall region and from the third sidewall region, etching the semiconductor substrate using the patterned mask to form fins, forming a gate stack over the fins, and forming source and drain regions in the fin adjacent the gate stack.

## Claims

### Claim 1

A method comprising:
depositing a mask layer over a semiconductor substrate;
etching the mask layer to form a patterned mask, wherein a sidewall of the patterned mask comprises a first sidewall region, a second sidewall region, and a third sidewall region, wherein the first sidewall region is farther from the semiconductor substrate than the second sidewall region and the second sidewall region is farther from the semiconductor substrate than the third sidewall region, wherein the second sidewall region protrudes laterally from the first sidewall region and from the third sidewall region;
etching the semiconductor substrate using the patterned mask to form fins;
forming a gate stack over the fins; and
forming source and drain regions in the fin adjacent the gate stack.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
depositing a polysilicon layer over the patterned mask and over the fins;
forming an isolation region surrounding the fins; and
removing the patterned mask.

### Claim 3 (depends on 2)

The method of claim 2, wherein depositing the polysilicon layer comprises a process temperature between 500° C. and 900° C.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second sidewall region protrudes laterally from the first sidewall region a lateral distance between 2 nm and 30 nm.

### Claim 5 (depends on 1)

The method of claim 1, wherein the mask layer comprises silicon nitride.

### Claim 6 (depends on 1)

The method of claim 1, further comprising depositing an oxide layer on the semiconductor substrate, wherein the mask layer is deposited on the oxide layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first sidewall region has a first width between 5 nm and 50 nm and the second sidewall region has a second width between 7 nm and 80 nm.

### Claim 8 (depends on 1)

The method of claim 1, wherein etching the mask layer comprises:
performing a first dry etch process to partially recess the mask layer;
after performing the first dry etch process, depositing a passivation layer over the mask layer; and
after depositing the passivation layer, performing a second dry etch process.

### Claim 9 (depends on 1)

The method of claim 1, further comprising performing an etching process on the patterned mask and the fins, wherein surfaces of the patterned mask and surfaces of the fins are rougher after performing the etching process than before performing the etching process.

### Claim 10

A method comprising:
forming a first mask layer over a semiconductor substrate;
forming a second mask layer over the first mask layer;
patterning the second mask layer;
etching the first mask layer through the patterned second mask layer to form a patterned first mask layer, the etching of the first mask layer comprising:
performing a first etching process to form upper portions of the patterned first mask layer, the upper portions having a first width;
after performing the first etching process, performing a second etching process to form middle portions of the patterned first mask layer, the middle portions having a second width greater than the first width, wherein the second etching process is different than the first etching process; and
after performing the second etching process, performing a third etching process to form lower portions of the patterned first mask layer, the lower portions having a third width less than the first width, wherein the third etching process is different than the second etching process; and
etching the semiconductor substrate through the patterned first mask layer to form a plurality of adjacent fins protruding from the semiconductor substrate.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second width is greater than a width of a fin of the plurality of adjacent fins.

### Claim 12 (depends on 10)

The method of claim 10, wherein adjacent fins of the plurality of adjacent fins are separated by a distance in the range of 5 nm and 50 nm.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first etching process, the second etching process, and the third etching process are plasma etching processes.

### Claim 14 (depends on 10)

The method of claim 10, further comprising depositing a passivation layer over the upper portions before performing the second etching process.

### Claim 15 (depends on 10)

The method of claim 10, wherein the thickness of the middle portions is between 5% and 33% of the thickness of the patterned mask layer.

### Claim 16

A method of forming a semiconductor device, the method comprising:
depositing a mask layer over a substrate;
patterning the mask layer to form a plurality of mask regions, wherein each mask region has convex sidewalls;
etching the substrate using the plurality of mask regions as an etching mask to form a plurality of fins, wherein after etching the substrate, the convex sidewalls of the mask regions extend laterally beyond upper sidewalls of the fins;
forming an isolation region surrounding the fins;
forming a gate structure over top surfaces of the fins and on the upper sidewalls of the fins; and
forming source and drain regions in the fin adjacent the gate structure.

### Claim 17 (depends on 16)

The method of claim 16, wherein the convex sidewalls extend a lateral distance between 2 nm and 30 nm beyond the upper sidewalls of the fins.

### Claim 18 (depends on 16)

The method of claim 16, wherein forming an isolation region comprises:
depositing an isolation material over the plurality of mask regions and surrounding the fins; and
performing a planarization process to expose top surfaces of the fins, the planarization process removing the plurality of mask regions.

### Claim 19 (depends on 16)

The method of claim 16, further comprising depositing an anti-reflective coating over the substrate before depositing the mask layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein the plurality of mask regions are between 10 nm and 30 nm thick.