# US 10,770,290 B2 · Method for forming stacked nanowire transistors

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- Number: US 10,770,290 B2
- Document ID: US10770290B2
- Status: Granted
- Kind: B2
- Application number: 16/033,401
- Filed: 2018-07-12
- Published: 2018-11-08
- Granted: 2020-09-08
- Earliest claimed: 2015-11-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tung Ying Lee; Shao-Ming Yu
- Web page: https://patentgrep.com/patent/US10770290B2

## CPC

- H10D 84/0128: {Manufacturing their channels}
- H10P 14/3462: {Nanowires}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/40: of conductive or resistive materials
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first semiconductor stack including elongated semiconductor features spaced apart from each other and overlaid in a direction perpendicular to a top surface of the substrate; and
a second semiconductor stack including elongated semiconductor features spaced apart from each other and overlaid in the direction perpendicular to the top surface of the substrate, the second semiconductor stack having different geometric characteristics than the first semiconductor stack, a top surface of a topmost elongated semiconductor feature of the first semiconductor stack being coplanar with a top surface of a topmost elongated semiconductor feature of the second semiconductor stack, wherein the topmost elongated semiconductor feature of the first semiconductor stack is formed of a different material than the topmost elongated semiconductor feature of the second semiconductor stack, wherein a bottommost elongated semiconductor feature from the first semiconductor stack is closer to the substrate than a bottommost elongated semiconductor feature from the second semiconductor stack without either bottommost elongated semiconductor features from the first or second semiconductor stacks physically directly contacting the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
an isolation feature disposed in the substrate adjacent the first semiconductor stack.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor stack has a different pitch than the second semiconductor stack.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the elongated semiconductor features of the first semiconductor stack have different thicknesses than the elongated semiconductor features of the second semiconductor stack.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein:
the first semiconductor stack has a smaller pitch than the second semiconductor stack; and
the elongated semiconductor features of the first semiconductor stack have smaller thicknesses than the elongated semiconductor features of the second semiconductor stack.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a number of the elongated semiconductor features of the first semiconductor stack is different than a number of the elongated semiconductor features of the second semiconductor stack.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the number of the elongated semiconductor features of the first semiconductor stack is twice of the number of the elongated semiconductor features of the second semiconductor stack.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the elongated semiconductor features of the first semiconductor stack have different cross-sectional shapes than the elongated semiconductor features of the second semiconductor stack.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein cross-sectional shapes of the elongated semiconductor features of the first and second semiconductor stacks are selected from rectangular, square, circular, elliptical, and diamond.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the elongated semiconductor features of the first semiconductor stack are also different from the elongated semiconductor features of the second semiconductor stack in material compositions.

### Claim 11

A semiconductor device, comprising:
a substrate;
a first nanowire stack including a first plurality of nanowires; and
a second nanowire stack including a second plurality of nanowires, wherein a nanowire of the first plurality of nanowires has a different thickness than a nanowire of the second plurality of nanowires, and wherein a top surface of a top-most nanowire of the first plurality of nanowires is coplanar with a top surface of a top-most nanowire of the second plurality of nanowires, wherein a bottommost nanowire from the first nanowire stack is closer to the substrate than a bottommost nanowire from the second nanowire stack without either bottommost nanowires from the first or second nanowire stacks directly contacting the substrate, wherein the bottommost nanowire from the second nanowire stack is thicker than the bottommost nanowire from the first nanowire stack, wherein the top-most nanowire of the first plurality of nanowires is formed of a different material than the top-most nanowire of the second plurality of nanowires.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first plurality of nanowires has a different pitch than the second plurality of nanowires.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first plurality of nanowires includes more elongated, vertically stacked features than the second plurality of nanowires.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the first plurality of nanowires has a number of nanowires different than that of the second plurality of nanowires.

### Claim 15

A semiconductor device, comprising:
a substrate;
a first nanowire stack including a first plurality of nanowires;
a second nanowire stack including a second plurality of nanowires, the second nanowire stack having different geometric characteristics than the first nanowire stack; and
an isolation feature disposed in the substrate adjacent the first nanowire stack, and
wherein a bottommost nanowire from the first plurality of nanowires is closer to the substrate than a bottommost nanowire from the second plurality of nanowires without either bottommost nanowires from the first or second plurality of nanowires directly contacting the substrate, wherein the bottommost nanowire from the second plurality of nanowires is thicker than the bottommost nanowire from the first plurality of nanowires, wherein the first plurality of nanowires has a different number of nanowires than the second plurality of nanowires.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first plurality of nanowires is different from the second plurality of nanowires in at least one of: pitch, nanowire thickness, or shape of nanowires.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein a top surface of a topmost nanowire of the first nanowire stack is coplanar with a top surface of a topmost nanowire of the second nanowire stack.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the first plurality of nanowires is formed from a material selected from the group consisting of a Si and SiGe, and
wherein the second plurality of nanowires is formed from a material selected from the group consisting of a Si and SiGe.

### Claim 19

The semiconductor of device 15, wherein each elongated semiconductor feature of the first semiconductor stack has a first thickness, wherein the first semiconductor stack is part of a first transistor in a single circuit, and
wherein each elongated semiconductor feature of the second semiconductor stack has a second thickness that is greater than the first thickness, wherein the second semiconductor stack is part of a second transistor in the single circuit, the second transistor performing a different function than the first transistor, wherein an input/output operation of the second transistor improves because of the thicker elongated semiconductor features of the second semiconductor stack.