# US 10,770,233 B2 · Multilayer ceramic capacitor and board having the same

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- Number: US 10,770,233 B2
- Document ID: US10770233B2
- Status: Granted
- Kind: B2
- Application number: 16/444,350
- Filed: 2019-06-18
- Published: 2019-10-03
- Granted: 2020-09-08
- Earliest claimed: 2015-01-06
- Assignees: Samsung Electro-Mechanics Co., Ltd.
- Applicants: Samsung Electro-Mechanics Co., Ltd.
- Inventors: Min Hee Hong; Chul Seung Lee; Won Seh Lee; Doo Young Kim; Chang Hoon Kim; Jae Yeol Choi; Hyeun Tea Yoon
- Web page: https://patentgrep.com/patent/US10770233B2

## CPC

- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H01G 4/0085: {Fried electrodes}
- H01G 4/1227: {based on alkaline earth titanates}
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H05K 3/3442: {having edge contacts, e.g. leadless chip capacitors, chip carriers}
- H05K 2201/10015: Non-printed capacitor
- H05K 2201/10636: Leadless chip, e.g. chip capacitor or resistor
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- Y02P 70/62: related technologies for production or treatment of textile or flexible materials or products thereof, including footwear
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A multilayer ceramic capacitor includes a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked and a margin portion disposed on outer surfaces of the active portion; and external electrodes disposed on outer surfaces of the ceramic body. The margin portion includes an inner half adjacent to the active portion and an outer half adjacent to the edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half.

## Claims

### Claim 1

A multilayer ceramic capacitor comprising:
a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked in a thickness direction and a margin portion disposed on outer surfaces of the active portion; and
external electrodes disposed on outer surfaces of the ceramic body,
wherein the margin portion includes an inner half adjacent to the active portion and an outer half adjacent to an edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half, and the porosity of the inner half is 0.06% to 2.0%, and the porosity of the outer half is 0.05% or less,
in margin portions disposed on upper and lower surfaces of the active portion in the thickness direction, average sizes of dielectric grains of the inner half and the outer half are different from each other, and
the inner half of the margin portion covering upper, lower and side surfaces of the active portion is made of a same composition.

### Claim 2 (depends on 1)

The multilayer ceramic capacitor of claim 1, wherein an average size of each pore in the inner half is 0.05 μm to 0.1 μm.

### Claim 3 (depends on 1)

The multilayer ceramic capacitor of claim 1, wherein an average size of each pore in the outer half is 0.015 μm to 0.03 μm.

### Claim 4

A board having a multilayer ceramic capacitor, comprising:
a printed circuit board on which a plurality of electrode pads are disposed; and
the multilayer ceramic capacitor installed on the printed circuit board,
wherein the multilayer ceramic capacitor includes a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked in a thickness direction and a margin portion disposed on outer surfaces of the active portion, and external electrodes disposed on outer surfaces of the ceramic body,
the margin portion includes an inner half adjacent to the active portion and an outer half adjacent to an edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half, and the porosity of the inner half is 0.06% to 2.0%, and the porosity of the outer half is 0.05% or less,
in margin portions disposed on upper and lower surfaces of the active portion in the thickness direction, average sizes of dielectric grains of the inner half and the outer half are different from each other, and
the inner half of the margin portion covering upper, lower and side surfaces of the active portion is made of a same composition.

### Claim 5 (depends on 4)

The board having a multilayer ceramic capacitor of claim 4, wherein an average size of each pore in the inner half is 0.05 μm to 0.1 μm.

### Claim 6 (depends on 4)

The board having a multilayer ceramic capacitor of claim 4, wherein an average size of each pore in the outer half is 0.015 μm to 0.03 μm.