# US 10,770,168 B2 · Memory sub-system with background scan and histogram statistics > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,168 B2 - Document ID: US10770168B2 - Status: Granted - Kind: B2 - Application number: 16/034,076 - Filed: 2018-07-12 - Published: 2020-01-16 - Granted: 2020-09-08 - Earliest claimed: 2018-07-12 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Gerald L. Cadloni; Bruce A. Liikanen - Web page: https://patentgrep.com/patent/US10770168B2 ## CPC - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD} - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 2029/0409: {Online test} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Several embodiments of systems incorporating memory sub-systems are disclosed herein. In one embodiment, a memory sub-system can include a memory component and a processing device configured to perform a background scan on a memory region of the memory component. In some embodiments, the background scan includes generating a bit error count (BEC) of a codeword saved on the memory region and saving statistical information corresponding to the BEC of the codeword to a histogram statistics log. In some embodiments, when the BEC of the codeword is greater than a BEC threshold, a refresh operation is scheduled for the memory region and/or logged. In these and other embodiments, when one or more error recovery error correction code (ECC) operations do not correct bit errors in the codeword, a refresh and/or retirement operation is schedule for the memory region and/or is logged. ## Claims ### Claim 1 A system, comprising: a memory component comprising a plurality of memory regions configured to store a plurality of codewords; and a processing device operably connected to the memory component, wherein the processing device is configured to generate a bit error count (BEC) of a first codeword of the plurality of codewords saved to a first memory region in the plurality of memory regions; and store statistical information corresponding to the BEC of the first codeword in a BEC histogram corresponding to the plurality of codewords, wherein storing the statistical information comprises incrementing a counter value of a bin of the BEC histogram corresponding to the BEC of the first codeword. ### Claim 2 (depends on 1) The system of claim 1 further comprising an error correction code (ECC) engine, and wherein the BEC of the first codeword is less than or equal to a BEC capability of the ECC engine. ### Claim 3 (depends on 1) The system of claim 1, wherein the first memory region is a memory block, a memory die, a memory page, a stripe of memory pages, or a superblock. ### Claim 4 (depends on 3) The system of claim 3, wherein the first memory region is a stripe of memory pages, and wherein the processing device is configured to select the first memory region from within an oldest, fully-programmed superblock in the memory component. ### Claim 5 (depends on 1) The system of claim 1, wherein the processing device is further configured to determine if one or more bit errors are present in the first codeword; and perform a limited subset of error recovery error correction code (ECC) operations available to the processing device on the first codeword in an event bit error(s) are present in the first codeword. ### Claim 6 (depends on 1) The system of claim 1, wherein the processing device is configured to generate the BEC of the first codeword and to store the statistical information corresponding to the BEC of the first codeword in response to a determination that the system is idle. ### Claim 7 (depends on 1) The system of claim 1, wherein the processing device is configured to generate the BEC of the first codeword and to store the statistical information corresponding to the BEC of the first codeword in response to a determination that a predetermined delay has elapsed since a previous operation to store statistical information in the BEC histogram was completed. ### Claim 8 (depends on 1) The system of claim 1, wherein the processing device is configured to generate the BEC of the first codeword and to store the statistical information corresponding to the BEC of the first codeword in response to a corresponding command received from a coupled host device. ### Claim 9 (depends on 1) The system of claim 1, wherein to generate the BEC of the first codeword, the processing device is configured to decode the first codeword of the plurality of codewords saved to the first memory region in the plurality of memory regions. ### Claim 10 (depends on 1) The system of claim 1, wherein the processing device is further configured to reset the BEC histogram in response to receiving a vender specific command in response to determining that a counter value stored in the BEC histogram reaches a maximum value, and/or after detecting a dynamic program target (DPT) update. ### Claim 11 A method, comprising: generating a bit error count (BEC) of a first codeword in a plurality of codewords saved to a first memory region in a plurality of memory regions; and storing statistical information corresponding to the BEC of the first codeword in a BEC histogram corresponding to the plurality of codewords, wherein storing the statistical information comprises incrementing a counter value of a bin of the BEC histogram corresponding to the BEC of the first codeword. ### Claim 12 (depends on 11) The method of claim 11 further comprising determining if one or more bit errors are present in the codeword; and performing a limited subset of available error recovery error correction code (ECC) operations on the first codeword in an event bit error(s) are present in the first codeword. ### Claim 13 (depends on 11) The method of claim 11 further comprising generating a BEC of a second codeword in the plurality of codewords saved to the first memory region or a second memory region in the plurality of memory regions; and storing statistical information corresponding to the BEC of the second codeword in the BEC histogram. ### Claim 14 (depends on 13) The method of claim 13, wherein generating the BEC of the second codeword includes generating the BEC of the second codeword a first time period after generating the BEC of the first codeword in accordance with a scheduled cadence. ### Claim 15 A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: generate a bit error count (BEC) of a first codeword in a plurality of codewords saved to a first memory region in a plurality of memory regions; and store statistical information corresponding to the BEC of the first codeword in a BEC histogram corresponding to the plurality of codewords, wherein storing the statistical information comprises incrementing a counter value of a bin of the BEC histogram corresponding to the BEC of the first codeword. ### Claim 16 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the processing device is further to: determine if one or more bit errors are present in the codeword; and perform a limited subset of available error recovery error correction code (ECC) operations on the first codeword in an event bit error(s) are present in the first codeword. ### Claim 17 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the processing device is further to: generate a BEC of a second codeword in the plurality of codewords saved to the first memory region or a second memory region in the plurality of memory regions; and store statistical information corresponding to the BEC of the second codeword in the BEC histogram.