# US 10,770,165 B1 · No-verify programming followed by short circuit test in memory device

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- Number: US 10,770,165 B1
- Document ID: US10770165B1
- Status: Granted
- Kind: B1
- Application number: 16/571,844
- Filed: 2019-09-16
- Granted: 2020-09-08
- Earliest claimed: 2019-09-16
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Xue Qing Cai; Jiahui Yuan; Deepanshu Dutta
- Web page: https://patentgrep.com/patent/US10770165B1

## CPC

- G11C 29/025: {in signal lines}
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4094: Bit-line management or control circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/5004: {Voltage}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Techniques are described for programming memory cells without performing a verify test, where the programming is followed by a short circuit test. In one aspect, an initial programming is performed on memory cells of a first word line of a block using a program pulse with an initial magnitude, Vpgm. By reading the memory cells, Vpgm can be optimized for programming subsequent word lines. The subsequent word lines may be programmed using a no-verify program operation followed by a word line short circuit test, for one or more word lines involved in the program operation. The short circuit test can be performed concurrently on a single word line, multiple word lines and/or one or more sub-blocks of a block, based on an amount of write data which can be storage by a controller.

## Claims

### Claim 1

An apparatus, comprising:
a set of word lines;
a plurality of memory cells, the memory cells are connected to the word lines;
a control circuit connected to the memory cells; and
a volatile storage connected to the control circuit, the volatile storage configured to store successive units of write data, one unit at a time, including a unit of write data for a first group of memory cells of the plurality of memory cells, the first group of memory cells is connected to one or more word lines of the set of word lines; and
the control circuit is configured to program the first group of memory cells using the unit of write data without performing a verify test, subsequently test the one or more word lines for a short circuit, and decide whether to replace the unit of write data for the first group of memory cells with a unit of write data for a next group of memory cells based on a result of the test.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit, to test for the short circuit, is configured to apply a test voltage to the one or more word lines and read pass voltages to remaining word lines of the set of word lines while determining whether there is a non-conductive memory cell among the first group of memory cells;
the test voltage is greater than the read pass voltage; and
the read pass voltages comprise a read pass voltage on a source side of the one or more word lines which is greater than a read pass voltage on a drain side of the one or more word lines.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
the first group of memory cells is connected to multiple word lines of the set of word lines;
the control circuit, to test for the short circuit, is configured to apply a test voltage to the multiple word lines and a read pass voltage to remaining word lines of the set of word lines while determining whether there is a non-conductive memory cell among the first group of memory cells; and
the test voltage is greater than the read pass voltage.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
the first group of memory cells is connected to a single word line of the set of word lines;
the control circuit, to test for the short circuit, is configured to apply a test voltage to the one word line and a read pass voltage to remaining word lines of the set of word lines while determining whether there is a non-conductive memory cell among the first group of memory cells; and
the test voltage is greater than the read pass voltage.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit is configured to replace the unit of write data for the first group of memory cells with the unit of write data for the next group of memory cells, and to program the next group of memory cells, in response to the test for the short circuit indicating there is no short circuit.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein:
the first group of memory cells encompasses a subset of one word line; and
the control circuit is configured to test for the short circuit in response to completing programming of memory cells in the first group of memory cells encompassing the subset of the one word line.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein:
the first group of memory cells encompasses a full word line of the one or more word lines and a subset of another word line of the one or more word lines; and
the control circuit is configured to program memory cells in the first group of memory cells encompassing the full word line before programming memory cells in the first group of memory encompassing the subset of the another word line, and to test for the short circuit in the full word line and the another word line in response to completing programming of the memory cells encompassing the subset of the another word line.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein:
the plurality of memory cells are arranged in a block, the block comprises a set of sub-blocks;
a set of bit lines is shared among the set of sub-blocks;
the first group of memory cells is connected to a single word line of the set of word lines, and is arranged in NAND strings in multiple sub-blocks of the set of sub-blocks; and
the control circuit, to test for the short circuit, is configured to concurrently:
connect the NAND strings in the multiple sub-blocks to the set of bit lines by providing respective select gate transistors of the NAND strings in the multiple sub-blocks in a conductive state;
apply a test voltage to the one or more word lines and a read pass voltage to remaining word lines of the set of word lines; and
sense currents on the set of bit lines to determine whether there is a non-conductive memory cell among the first group of memory cells.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein:
the control circuit, to test for the short circuit, is configured to disconnect NAND strings in one or more remaining sub-blocks of the set of sub-blocks from the set of bit lines by providing respective select gate transistors of the NAND strings in the one or more remaining sub-blocks of the set of sub-blocks in a non-conductive state.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein:
the test voltage is greater when a number of sub-blocks in the multiple sub-blocks is lower.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein:
to program the first group of memory cells using the unit of write data without performing a verify test, the control circuit is configured to apply a single program pulse having an initial magnitude to the first group of memory cells; and
the control circuit is configured to evaluate an upper tail of a threshold voltage distribution of the first group of memory cells after the programming of the first group of memory cells, determine an adjusted magnitude which is greater than the initial magnitude in response to the evaluating, and apply an additional program pulse having the adjusted magnitude to the first group of memory cells without performing a verify test.

### Claim 12

A method, comprising:
storing write data for a first group of memory cells of a block in a volatile storage, the first group of memory cells is connected to multiple word lines of a set of word lines;
programming the first group of memory cells using the write data without performing a verify test;
in response to completion of the programming, concurrently testing the multiple word lines for a short circuit; and
in response to the testing indicating that there is no short circuit, replacing the write data for the first group of memory cells with write data for a next group of memory cells of the block and programming the next group of memory cells of the block.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the testing comprises applying a test voltage to the multiple word lines and a read pass voltage to remaining word lines of the set of word lines while determining whether there is a non-conductive memory cell among the first group of memory cells.

### Claim 14 (depends on 13)

The method of claim 13, wherein:
the test voltage is greater than the read pass voltage.

### Claim 15 (depends on 12)

The method of claim 12, wherein:
the block comprises a set of sub-blocks;
the first group of memory cells are arranged in NAND strings in multiple sub-blocks of the set of sub-blocks;
a set of bit lines is shared among the set of sub-blocks; and
the testing comprises concurrently:
connecting the NAND strings in the multiple sub-blocks to the set of bit lines;
applying a test voltage to the multiple word lines and a read pass voltage to remaining word lines of the set of word lines; and
sensing currents on the set of bit lines to determine whether there is a non-conductive memory cell among the first group of memory cells.

### Claim 16

An apparatus, comprising:
a set of word lines;
a block of memory cells, the memory cells are connected to the set of word lines and include memory cells connected to an initial word line of the block; and
a control circuit connected to the memory cells, the control circuit is configured to apply a first single program pulse having an initial magnitude to the initial word line, obtain a count of number of the memory cells connected to the initial word line having a threshold voltage greater than a read voltage, determine an adjusted magnitude which is greater than the initial magnitude based on the count, and apply a second single program pulse having the adjusted magnitude to the initial word line without performing a verify test, to complete programming of the memory cells connected to an initial word line.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein:
the control circuit is configured to apply a single program pulse having the adjusted magnitude to another word line in the block without performing a verify test, and to perform a short circuit test of the another word line to determine whether programming of memory cells connected to the another word lines is successfully completed.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein:
to perform the short circuit test, the control circuit is configured to apply a test voltage to the another word line and a read pass voltage to remaining word lines of the set of word lines while determining whether there is a non-conductive memory cell among memory cells connected to the another word line; and
the test voltage is greater than the read pass voltage.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein:
the memory cells of the block are arranged in NAND strings;
the NAND strings comprise respective pillars having a width which varies along a height in the block; and
the test voltage is an increasing function of a width of the respective pillars adjacent to the another word line.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein:
the test voltage is greater than the read pass voltage.