# US 10,770,163 B2 · Shift register unit, method of driving shift register unit, gate driving circuit and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,163 B2 - Document ID: US10770163B2 - Status: Granted - Kind: B2 - Application number: 16/158,735 - Filed: 2018-10-12 - Published: 2019-10-03 - Granted: 2020-09-08 - Earliest claimed: 2018-03-30 - Assignees: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd. - Applicants: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd. - Inventors: Zhichong Wang - Web page: https://patentgrep.com/patent/US10770163B2 ## CPC - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G11C: STATIC STORES (semiconductor memory devices H10B) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A shift register unit, a method of driving a shift register unit, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a first pull-up node reset circuit and an output circuit. The input circuit is configured to control an level of a pull-up node to a first level in response to an input signal of an input terminal, and thereafter control a level of a first node to a second level under control of a level of a pull-down node. The first node is in a current path for controlling the level of the pull-up node. The first pull-up node reset circuit is configured to reset the pull-up node in response to a first reset signal. The output circuit is configured to output a clock signal to an output terminal under control of the level of the pull-up node. ## Claims ### Claim 1 A shift register unit, comprising an input circuit, a first pull-up node reset circuit, and an output circuit; wherein the input circuit comprises an input terminal, and is configured to control an level of a pull-up node to a first level in response to an input signal of the input terminal, and thereafter control a level of a first node to a second level under control of a level of a pull-down node, in which the first node is in a current path for controlling the level of the pull-up node; the first pull-up node reset circuit is configured to reset the pull-up node in response to a first reset signal; and the output circuit is configured to output a clock signal to an output terminal under control of the level of the pull-up node; the input circuit comprises a first input sub-circuit, a second input sub-circuit, and a first node control sub-circuit; the first input sub-circuit is configured to control the level of the first node to the first level in response to the input signal; the second input sub-circuit is configured to control the level of the pull-up node to the first level in response to the input signal; and the first node control sub-circuit is configured to control the level of the first node to the second level under control of the level of the pull-down node. ### Claim 2 (depends on 1) The shift register unit according to claim 1, wherein the first input sub-circuit comprises: a first transistor, in which a gate electrode of the first transistor is configured to be connected to the input terminal to receive the input signal, a first electrode of the first transistor is configured to be connected to a first voltage terminal to receive a first voltage, and a second electrode of the first transistor is configured to be connected to the first node; the second input sub-circuit comprises: a second transistor, in which a gate electrode of the second transistor is configured to be connected to the input terminal to receive the input signal, a first electrode of the second transistor is configured to be connected to the first node, and a second electrode of the second transistor is configured to be connected to the pull-up node; and the first node control sub-circuit comprises: a third transistor, in which a gate electrode of the third transistor is configured to be connected to the pull-down node, a first electrode of the third transistor is configured to be connected to the first node, and a second electrode of the third transistor is configured to be connected to a second voltage terminal to receive a second voltage. ### Claim 3 (depends on 1) The shift register unit according to claim 1, further comprising a pull-down circuit, a pull-down control circuit, a pull-up node noise reduction circuit, and an output noise reduction circuit; wherein the pull-down circuit is configured to control the level of the pull-down node under control of the level of the pull-up node and a level of a pull-down control node; the pull-down control circuit is configured to control the level of the pull-down control node under control of the level of the pull-up node; the pull-up node noise reduction circuit is configured to perform noise reduction on the pull-up node under control of the level of the pull-down node; and the output noise reduction circuit is configured to perform noise reduction on the output terminal under control of the level of the pull-down node. ### Claim 4 (depends on 3) The shift register unit according to claim 3, wherein the pull-down circuit comprises an eighth transistor and a ninth transistor; a gate electrode of the eighth transistor is configured to be connected to the pull-down control node, a first electrode of the eighth transistor is configured to be connected to a clock signal terminal to receive the clock signal, and a second electrode of the eighth transistor is configured to be connected to the pull-down node; and a gate electrode of the ninth transistor is configured to be connected to the pull-up node, a first electrode of the ninth transistor is configured to be connected to the pull-down node, and a second electrode of the ninth transistor is configured to be connected to a second voltage terminal to receive a second voltage. ### Claim 5 (depends on 3) The shift register unit according to claim 3, wherein the pull-down control circuit comprises a tenth transistor and an eleventh transistor; a gate electrode of the tenth transistor is connected to a first electrode of the tenth transistor and configured to be connected to a clock signal terminal to receive the clock signal, and a second electrode of the tenth transistor is configured to be connected to the pull-down control node; and a gate electrode of the eleventh transistor is configured to be connected to the pull-up node, a first electrode of the eleventh transistor is configured to be connected to the pull-down control node, and a second electrode of the eleventh transistor is configured to be connected to a second voltage terminal to receive a second voltage. ### Claim 6 (depends on 3) The shift register unit according to claim 3, wherein the pull-up node noise reduction circuit comprises a twelfth transistor; and a gate electrode of the twelfth transistor is configured to be connected to the pull-down node, a first electrode of the twelfth transistor is configured to be connected to the pull-up node, and a second electrode of the twelfth transistor is configured to be connected to a second voltage terminal to receive a second voltage. ### Claim 7 (depends on 3) The shift register unit according to claim 3, wherein the output noise reduction circuit comprises a thirteenth transistor; and a gate electrode of the thirteenth transistor is configured to be connected to the pull-down node, a first electrode of the thirteenth transistor is configured to be connected to the output terminal, and a second electrode of the thirteenth transistor is configured to be connected to a second voltage terminal to receive a second voltage. ### Claim 8 (depends on 1) The shift register unit according to claim 1, wherein the first pull-up node reset circuit is further configured to control a level of a second node to the second level under control of the level of the pull-down node, and the second node is in a reset path for resetting the pull-up node. ### Claim 9 (depends on 8) The shift register unit according to claim 8, wherein the first pull-up node reset circuit comprises a first reset sub-circuit, a second reset sub-circuit, and a second node control sub-circuit; the first reset sub-circuit is configured to reset the second node in response to the first reset signal; the second reset sub-circuit is configured to reset the pull-up node in response to the first reset signal; and the second node control sub-circuit is configured to control the level of the second node to the second level under control of the level of the pull-down node. ### Claim 10 (depends on 9) The shift register unit according to claim 9, wherein the first reset sub-circuit comprises: a fourth transistor, in which a gate electrode of the fourth transistor is configured to be connected to a first reset terminal to receive the first reset signal, a first electrode of the fourth transistor is configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the fourth transistor is configured to be connected to the second node; the second reset sub-circuit comprises: a fifth transistor, in which a gate electrode of the fifth transistor is configured to be connected to the first reset terminal to receive the first reset signal, a first electrode of the fifth transistor is configured to be connected to the second node, and a second electrode of the fifth transistor is configured to be connected to the pull-up node; and the second node control sub-circuit comprises: a sixth transistor, in which a gate electrode of the sixth transistor is configured to be connected to the pull-down node, a first electrode of the sixth transistor is configured to be connected to the second node, and a second electrode of the sixth transistor is configured to be connected to a second voltage terminal to receive a second voltage. ### Claim 11 (depends on 8) A method of driving the shift register unit according to claim 8, wherein the input signal and the first reset signal are exchanged with each other, and the method comprises: in a first phase, the first pull-up node reset circuit controls the level of the pull-up node to the first level in response to the input signal, and the output circuit outputs a third level of the clock signal to the output terminal; in a second phase, the output circuit outputs a fourth level of the clock signal to the output terminal; in a third phase, the input circuit resets the pull-up node under control of the first reset signal; and in a fourth phase, the first pull-up node reset circuit controls the level of the second node to the second level under control of the level of the pull-down node. ### Claim 12 (depends on 1) The shift register unit according to claim 1, wherein the output circuit comprises a seventh transistor and a first capacitor; a gate electrode of the seventh transistor is configured to be connected to the pull-up node, a first electrode of the seventh transistor is configured to be connected to a clock signal terminal to receive the clock signal, and a second electrode of the seventh transistor is configured to be connected to the output terminal; and a first electrode of the first capacitor is configured to be connected to the gate electrode of the seventh transistor, and a second electrode of the first capacitor is configured to be connected to the second electrode of the seventh transistor. ### Claim 13 (depends on 1) The shift register unit according to claim 1, further comprising a second pull-up node reset circuit; wherein the second pull-up node reset circuit is configured to reset the pull-up node in response to a second reset signal. ### Claim 14 (depends on 13) The shift register unit according to claim 13, wherein the second pull-up node reset circuit comprises a fourteenth transistor; and a gate electrode of the fourteenth transistor is configured to be connected to a second reset terminal to receive the second reset signal, a first electrode of the fourteenth transistor is configured to be connected to the pull-up node, and a second electrode of the fourteenth transistor is configured to be connected to a second voltage terminal to receive a second voltage. ### Claim 15 (depends on 1) The shift register unit according to claim 1, further comprising an output reset circuit; wherein the output reset circuit is configured to reset the output terminal in response to a second reset signal. ### Claim 16 (depends on 15) The shift register unit according to claim 15, wherein the output reset circuit comprises a fifteenth transistor; and a gate electrode of the fifteenth transistor is configured to be connected to a second reset terminal to receive the second reset signal, a first electrode of the fifteenth transistor is configured to be connected to the output terminal, and a second electrode of the fifteenth transistor is configured to be connected to a second voltage terminal to receive a second voltage. ### Claim 17 (depends on 1) A gate driving circuit, comprising the shift register unit according to claim 1. ### Claim 18 (depends on 17) A display device, comprising the gate driving circuit according to claim 17. ### Claim 19 (depends on 1) A method of driving the shift register unit according to claim 1, comprising: in a first phase, the input circuit controlling the level of the pull-up node to the first level in response to the input signal, and the output circuit outputting a third level of the clock signal to the output terminal; in a second phase, the output circuit outputting a fourth level of the clock signal to the output terminal; in a third phase, the first pull-up node reset circuit resetting the pull-up node under control of the first reset signal; and in a fourth phase, the input circuit controlling the level of the first node to the second level under control of the level of the pull-down node.