# US 10,770,154 B2 · Semiconductor memory devices and memory systems having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,154 B2 - Document ID: US10770154B2 - Status: Granted - Kind: B2 - Application number: 16/294,058 - Filed: 2019-03-06 - Published: 2020-03-12 - Granted: 2020-09-08 - Earliest claimed: 2018-09-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seong-Heon Yu; Joung Yeal Kim; Chul Ung Kim; Hyun Bo Kim; Joo Youn Lim - Web page: https://patentgrep.com/patent/US10770154B2 ## CPC - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/1087: {Data input latches} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 8/10: Decoders - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/20: Initialising; Data preset; Chip identification - G11C 29/781: {combined in a redundant decoder} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level, an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation, and a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command. ## Claims ### Claim 1 A semiconductor memory device comprising: a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level; an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation; a memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command; and a command/address generator configured to receive a clock enable signal and a chip selection signal in response to a clock signal and generate a power-down exit command, wherein the initializer is configured to generate the initial refresh command when the initialization operation is completed at a third time point before a first time point at which the power-down exit command is generated and after a second time point at which the clock signal is applied. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the semiconductor memory device further comprises a initialization operation unit that is configured to receive the initialization signal from the initializer and is configured to perform the initialization operation in response to the initialization signal from the initializer, wherein the initializer is configured to generate the initial refresh command when the initialization operation of the initialization operation unit is completed. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the command/address generator is configured to decode the chip selection signal and a command signal in response to the clock signal and to further generate a refresh command, an active command, a write command, a read command, or a mode setting command, to generate a row address from an address signal in response to the active command, to generate a column address from the address signal in response to the write command or the read command, and to generate a mode setting code from the address signal in response to the mode setting command, wherein the semiconductor memory device is configured to complete the initial refresh operation at a fifth time point between the first time point and a fourth time point at which the mode setting command is applied or at a seventh time point between the first time point and a sixth time point at which a mode setting operation is ended in response to the mode setting command. ### Claim 4 (depends on 3) The semiconductor memory device of claim 3, further comprising: a refresh row address generator configured to generate a refresh row address in response to the initial refresh command or the refresh command; a row address generator configured to generate a row address signal from the refresh row address in response to the initial refresh command or the refresh command or generate the row address signal from the row address in response to the active command; a row decoder configured to decode the row address signal in response to the initial refresh command or the refresh command and activate at least two word line selection signals or decode the row address signal in response to the active command and activate at least one word line selection signal; and a column decoder configured to decode a column address signal in response to the write command or the read command and activate at least one column selection signal. ### Claim 5 (depends on 4) The semiconductor memory device of claim 4, wherein the memory cell array comprises: a plurality of memory cell array blocks comprising a plurality of memory cells connected between the plurality of word lines and the plurality of bit lines; and a plurality of sense amplification blocks between the plurality of memory cell array blocks and configured to amplify data of the plurality of bit lines, wherein, responsive to at least two word lines of at least two of the memory cell array blocks being selected in response to the at least two word line selection signals in the initial refresh operation, the sense amplification blocks that are on both sides of each of the at least two memory cell array blocks are configured to amplify and store data stored in the memory cells connected to the at least two word lines. ### Claim 6 A semiconductor memory device comprising: a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level; an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command and an initial write command in response to completion of an initialization operation; an initial data driver configured to drive initial data in response to the initial write command; and a memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial write operation of writing the initial data to the plurality of memory cells in response to the initial refresh command and the initial write command. ### Claim 7 (depends on 6) The semiconductor memory device of claim 6, further comprising a command/address generator configured to receive a clock enable signal and a chip selection signal in response to a clock signal and generate a power-down exit command, wherein the initializer is configured to generate the initial refresh command and the initial write command in response to the initialization operation being completed at a third time point before a first time point at which the power-down exit command is applied and after a second time point at which the clock signal is applied. ### Claim 8 (depends on 7) The semiconductor memory device of claim 7, further comprising an initialization operation unit configured to perform the initialization operation in response to the initialization signal, wherein the initializer generates the initial refresh command and the initial write command in response to the completion of the initialization operation of the initialization operation unit. ### Claim 9 (depends on 7) The semiconductor memory device of claim 7, wherein the command/address generator is configured to decode the chip selection signal and a command signal in response to the clock signal and to further generate a refresh command, an active command, a write command, a read command, or a mode setting command, to generate a row address from an address signal in response to the active command, to generate a column address from the address signal in response to the write command or the read command, and to generate a mode setting code from the address signal in response to the mode setting command, wherein the semiconductor memory device is configured to complete the initial write operation at a fifth time point between the first time point and a fourth time point at which the mode setting command is applied or at a seventh time point between the first time point and a sixth time point at which a mode setting operation is ended in response to the mode setting command. ### Claim 10 (depends on 9) The semiconductor memory device of claim 9, further comprising: a refresh row address generator configured to generate a refresh row address in response to the initial refresh command or the refresh command; a row address generator configured to generate a row address signal from the refresh row address in response to the initial refresh command or the refresh command or generate the row address signal from the row address in response to the active command; a row decoder configured to decode the row address signal in response to the initial refresh command or the refresh command and activate at least two word line selection signals or to decode the row address signal in response to the active command and activate at least one word line selection signal; and a column decoder configured to activate all of a plurality of column selection signals in response to the initial write command or to decode a column address signal in response to the write command or the read command and activate at least one column selection signal. ### Claim 11 (depends on 10) The semiconductor memory device of claim 10, further comprising: a plurality of memory cell array blocks comprising a plurality of memory cells connected between the plurality of word lines and the plurality of bit lines; and a plurality of sense amplification blocks between the plurality of memory cell array blocks and configured to amplify data of the plurality of bit lines, wherein at least two word lines of at least two of the memory cell array blocks are selected in response to the at least two word line selection signals in the initial write operation, and the sense amplification blocks disposed on both sides of each of the at least two memory cell array blocks are configured to write the initial data to the memory cells connected to the at least two word lines. ### Claim 12 (depends on 7) The semiconductor memory device of claim 7, wherein the initial data driver comprises: a first driver configured to drive first initial data in the initial write operation; and a second driver configured to drive second initial data in the initial write operation. ### Claim 13 (depends on 7) The semiconductor memory device of claim 7, wherein the initial data driver comprises: a first latch configured to initialize a first node to a first initial value in response to the initialization signal and to latch the first initial value or input data; a second latch configured to initialize a second node to a second initial value in response to the initialization signal and to latch the second initial value or inverted input data; a first driver configured to drive the first initial value in the initial write operation or to drive the input data in a normal operation; and a second driver configured to drive the second initial value in the initial write operation or to drive the inverted input data in the normal operation. ### Claim 14 A memory system comprising: a controller configured to generate a reset signal in response to a power-up operation signal or a reset operation signal; and a memory configured to receive the reset signal, wherein the memory comprises: a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level; an initializer configured to generate an initialization signal in response to the power-up signal and the reset signal and to generate an initial refresh command in response to completion of an initialization operation; and a memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command. ### Claim 15 (depends on 14) The memory system of claim 14, wherein the initializer is configured to further generate an initial write command in response to an initialization completion signal, wherein the memory further comprises an initial data driver configured to drive initial data in response to the initial write command, and wherein the memory cell array is configured to perform an initial write operation of writing the initial data to the plurality of memory cells in response to the initial refresh command and the initial write command. ### Claim 16 (depends on 15) The memory system of claim 15, wherein the memory further comprises a command/address generator configured to receive a clock enable signal and a chip selection signal from the controller in response to a clock signal applied from the controller and generate a power-down exit command, wherein the initializer is configured to generate the initial refresh command or to generate the initial refresh command and the initial write command in response to the completion of the initialization operation at a third time point before a first time point at which the power-down exit command is applied and after a second time point at which the clock signal is applied. ### Claim 17 (depends on 16) The memory system of claim 16, wherein the memory further comprises an initialization operation unit configured to perform the initialization operation in response to the initialization signal, wherein the initializer is configured to generate the initial refresh command or to generate the initial refresh command and the initial write command in response to the completion of the initialization operation of the initialization operation unit. ### Claim 18 (depends on 16) The memory system of claim 16, wherein the command/address generator is configured to decode the chip selection signal and a command signal in response to the clock signal and further generates a refresh command, an active command, a write command, a read command, or a mode setting command, to generate a row address from an address signal included in the command/address in response to the active command, generates a column address from the address signal in response to the write command or the read command, and generates a mode setting code from the address signal in response to the mode setting command, wherein the memory completes the initial refresh operation or the initial write operation at a fifth time point between the first time point and a fourth time point at which the mode setting command is applied or at a seventh time point between the first time point and a sixth time point at which a mode setting operation is ended in response to the mode setting command. ### Claim 19 (depends on 18) The memory system of claim 18, wherein the memory cell array comprises: a plurality of memory cell array blocks comprising a plurality of memory cells connected between the plurality of word lines and the plurality of bit lines; and a plurality of sense amplification blocks disposed between the plurality of memory cell array blocks and configured to amplify data of the plurality of bit lines, wherein responsive to at least two word lines of at least two of the memory cell array blocks being selected in response to at least two word line selection signals in the initial refresh operation or the initial write operation, the sense amplification blocks disposed on both sides of each of the at least two memory cell array blocks amplify and store data stored in the memory cells connected to the at least two word lines or amplify and store the initial data.