# US 10,770,152 B2 · Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,152 B2 - Document ID: US10770152B2 - Status: Granted - Kind: B2 - Application number: 16/180,137 - Filed: 2018-11-05 - Published: 2019-03-07 - Granted: 2020-09-08 - Earliest claimed: 2012-04-17 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Kenneth J. Eldredge; Frankie F. Roohparvar; Luca De Santis; Tommaso Vali - Web page: https://patentgrep.com/patent/US10770152B2 ## CPC - G11C 16/28: using differential sensing or reference cells, e.g. dummy cells - G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores - G11C 15/046: {using non-volatile storage elements} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference. ## Claims ### Claim 1 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line while each string of series-connected memory cells of the plurality of strings of series-connected memory cells is concurrently electrically connected to the data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance in series with a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance in series with a different string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than the reference; and deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference. ### Claim 2 (depends on 1) The method of claim 1, wherein generating the respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating the respective resistance in series with the particular string of series-connected memory cells of the plurality of strings of series-connected memory cells to be different than the respective resistance in series with more than one different string of series-connected memory cells of the plurality of strings of series-connected memory cells. ### Claim 3 (depends on 1) The method of claim 1, wherein generating the respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating the respective resistance in series with any string of series-connected memory cells of the plurality of strings of series-connected memory cells to be different than the respective resistance in series with each remaining string of series-connected memory cells of the plurality of strings of series-connected memory cells. ### Claim 4 (depends on 1) The method of claim 1, wherein, for each string of series-connected memory cells of the plurality of strings of series-connected memory cells, generating the respective resistance in series with that string of series-connected memory cells comprises setting a respective resistor coupled to that string of series-connected memory cells to the respective resistance. ### Claim 5 (depends on 4) The method of claim 4, wherein setting the respective resistor coupled to that string of series-connected memory cells to the respective resistance comprises programming a respective transistor to have a respective threshold voltage. ### Claim 6 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance in series with a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance in series with a different string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than the reference; deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference; and deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being equal to the reference. ### Claim 7 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance in series with a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance in series with a different string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than the reference; and deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference; wherein generating the respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating a first resistance through a first set of transistors in series with a first string of series-connected memory cells of the plurality of strings of series-connected memory cells and generating a second resistance through a second set of transistors in series with a second string of series-connected memory cells of the plurality of strings of series-connected memory cells, wherein the first resistance is less than the second resistance. ### Claim 8 (depends on 7) The method of claim 7, wherein generating the first resistance through the first set of transistors in series with a first string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating the first resistance through the first set of transistors having one or more transistors in series with the first string of series-connected memory cells. ### Claim 9 (depends on 7) The method of claim 7, wherein generating the first resistance and generating the second resistance comprises generating the second resistance to be substantially a factor of two greater than the first resistance. ### Claim 10 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance in series with a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance in series with a different string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than the reference; and deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference; wherein generating the respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating a first resistance in series with a first string of series-connected memory cells of the plurality of strings of series-connected memory cells having N strings of series-connected memory cells, and, for each remaining string of series-connected memory cells of the N strings of series-connected memory cells corresponding to a respective number X from 2 through N, generating the respective resistance in series with that string of series-connected memory cells to have a respective value of substantially 2{circumflex over ( )}X times the first resistance. ### Claim 11 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line while each string of series-connected memory cells of the plurality of strings of series-connected memory cells is concurrently electrically connected to the data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance in series with any string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance in series with any other string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than or equal to the reference; and deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference. ### Claim 12 (depends on 11) The method of claim 11, wherein generating the respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating a first resistance through a first set of transistors in series with a first string of series-connected memory cells of the plurality of strings of series-connected memory cells and generating a second resistance through a second set of transistors in series with a second string of series-connected memory cells of the plurality of strings of series-connected memory cells. ### Claim 13 (depends on 12) The method of claim 12, wherein generating the first resistance through the first set of transistors in series with a first string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating the first resistance through the first set of transistors comprising one or more transistors in series. ### Claim 14 (depends on 11) The method of claim 11, wherein, for each string of series-connected memory cells of the plurality of strings of series-connected memory cells, generating the respective resistance in series with that string of series-connected memory cells comprises setting a respective resistor coupled to that string of series-connected memory cells to the respective resistance. ### Claim 15 (depends on 14) The method of claim 14, wherein setting the respective resistor coupled to that string of series-connected memory cells to the respective resistance comprises programming a respective transistor to have a respective threshold voltage. ### Claim 16 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance in series with any string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance in series with any other string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than or equal to the reference; and deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference; wherein generating the respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating a first resistance through a first set of transistors in series with a first string of series-connected memory cells of the plurality of strings of series-connected memory cells and generating a second resistance through a second set of transistors in series with a second string of series-connected memory cells of the plurality of strings of series-connected memory cells; and wherein generating the first resistance and generating the second resistance comprises generating the second resistance to be substantially a factor of two greater than the first resistance. ### Claim 17 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line while each string of series-connected memory cells of the plurality of strings of series-connected memory cells is concurrently electrically connected to the data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance through a respective set of transistors in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance through the respective set of transistors in series with a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance through the respective set of transistors in series with a different string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than or equal to the reference; and deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference. ### Claim 18 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance through a respective set of transistors in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance through the respective set of transistors in series with a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance through the respective set of transistors in series with a different string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than or equal to the reference; and deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference; wherein generating the respective resistance through the respective set of transistors in series with a first string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating a particular resistance that is greater than the respective resistance through the respective set of transistors in series with a second string of series-connected memory cells of the plurality of strings of series-connected memory cells. ### Claim 19 (depends on 18) The method of claim 18, wherein generating the particular resistance that is greater than the respective resistance through the respective set of transistors in series with the second string of series-connected memory cells comprises generating the particular resistance that is a factor of two greater than the respective resistance through the respective set of transistors in series with the second string of series-connected memory cells. ### Claim 20 A method of operating a memory device, comprising: comparing a plurality of digits of input data to data stored in memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of data of the plurality of digits of input data is compared to a respective digit of data stored in memory cells of the plurality of strings of series-connected memory cells, and wherein each respective digit of data is stored in memory cells of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; generating a respective resistance through a respective set of transistors in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells while comparing the plurality of digits of input data to the data stored in the memory cells of the plurality of strings of series-connected memory cells, wherein the respective resistance through the respective set of transistors in series with a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells is different than the respective resistance through the respective set of transistors in series with a different string of series-connected memory cells of the plurality of strings of series-connected memory cells; comparing a representation of a level of current in the data line to a reference; deeming the plurality of digits of input data to match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being less than or equal to the reference; and deeming the plurality of digits of input data to not match the data stored in the memory cells of the plurality of strings of series-connected memory cells in response to the representation of the level of current in the data line being greater than the reference; wherein generating the respective resistance in series with each string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises generating a first resistance in series with a first string of series-connected memory cells of the plurality of strings of series-connected memory cells having N strings of series-connected memory cells, and, for each remaining string of series-connected memory cells of the N strings of series-connected memory cells corresponding to a respective integer X from 2 through N, generating the respective resistance in series with that string of series-connected memory cells to have a respective value of substantially 2{circumflex over ( )}(X−1) times the first resistance.