# US 10,770,151 B2 · Semiconductor memory device and operating method thereof

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- Number: US 10,770,151 B2
- Document ID: US10770151B2
- Status: Granted
- Kind: B2
- Application number: 16/749,630
- Filed: 2020-01-22
- Published: 2020-05-21
- Granted: 2020-09-08
- Earliest claimed: 2017-10-18
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong Uk Lee; Jae Hyuk Bang
- Web page: https://patentgrep.com/patent/US10770151B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 29/021: {in voltage or current generators}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5635: {Erasing circuits}
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 2211/5631: Concurrent multilevel reading of more than one cell
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.

## Claims

### Claim 1

A method for operating a semiconductor memory device including a plurality of memory blocks, the method comprising:
receiving a read command for a memory block among the plurality of memory blocks;
referring to a block read count value corresponding to the memory block;
determining whether the block read count value has reached a threshold value; and
performing a read operation on the memory block based on a result of the determining operation,
wherein the performing of the read operation on the memory block when it is determined that the block read count value reaches the threshold value, includes:
performing a threshold voltage increase operation on a select program state of the memory block; and
performing the read operation on the memory block.

### Claim 2 (depends on 1)

The method of claim 1, wherein the performing of the read operation on the memory block when it is determined that the block read count value does not reach the threshold value, includes:
performing the read operation on the memory block.

### Claim 3 (depends on 2)

The method of claim 2, wherein the performing of the threshold voltage increase operation on the select program state of the memory block includes:
applying a program permission voltage to a bit line coupled to a first memory cell having the select program state among memory cells included in a first page of the memory block;
applying a program prohibition voltage to a bit line coupled to a second memory cell instead of the first memory cell among the memory cells included in the first page; and
applying a third voltage having a positive value to a word line coupled to the memory cells included in the first page.

### Claim 4 (depends on 3)

The method of claim 3, wherein the third voltage is determined to allow a threshold voltage of the first memory cell to drift.

### Claim 5 (depends on 4)

The method of claim 4, further comprising, after performing the read operation on the memory block, increasing the block read count value of the memory block.

### Claim 6

A semiconductor memory device comprising:
a memory cell array including a plurality of memory blocks;
a peripheral circuit configured to perform any one of a read operation, a write operation, and an erase operation on the memory cell array;
a block read counter configured to store a block read count value of each of the plurality of memory blocks; and
control logic configured to control operations of the peripheral circuit and the block read counter,
wherein, when a read command for a memory block among the plurality of memory blocks is received, the control logic controls the peripheral circuit and the block read counter to perform a read operation on the memory block, based on a block read count value of the memory block,
wherein, when the block read count value of the memory block reaches a second threshold value,
the control logic controls the peripheral circuit to increase a threshold voltage distribution in a select program state of the memory block and perform the read operation on the memory block.

### Claim 7 (depends on 6)

The semiconductor memory device of claim 6, wherein, when the block read count value of the memory block does not reach the second threshold value,
the control logic controls the peripheral circuit to perform the read operation on the memory block.

### Claim 8 (depends on 7)

The semiconductor memory device of claim 7, wherein an increase in threshold voltage distribution on the select program state of the memory block is performed by applying a program permission voltage to a bit line coupled to a first memory cell having the select program state among memory cells included in a first page of the memory block, applying a program prohibition voltage to a bit line coupled to a second memory cell instead of the first memory cell among the memory cells included in the first page, and applying a third voltage having a positive value to a word line coupled to the memory cells including in the first page.

### Claim 9 (depends on 6)

The semiconductor memory device of claim 6, wherein, after the read operation on the memory block is performed, the control logic controls the block read counter to increase the block read count value.