# US 10,770,147 B2 · Memory system including a memory device that can determine optimum read voltage applied to a word line > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,147 B2 - Document ID: US10770147B2 - Status: Granted - Kind: B2 - Application number: 15/446,952 - Filed: 2017-03-01 - Published: 2018-03-29 - Granted: 2020-09-08 - Earliest claimed: 2016-09-29 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Shohei Asami; Toshikatsu Hida - Web page: https://patentgrep.com/patent/US10770147B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 29/028: {with adaption or trimming of parameters} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 2029/1202: {Word line control} - H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes} - H03M 13/1515: {Reed-Solomon codes} - H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line. ## Claims ### Claim 1 A memory system comprising: a nonvolatile memory including a word line and a plurality of memory cells connected to the word line; and a controller configured to: perform a first threshold voltage tracking operation, during which the controller determines an optimum read voltage for the plurality of memory cells connected to the word line based on data read from the plurality of memory cells using multiple read voltages; calculate an exhaustion degree of the plurality of memory cells connected to the word line based on the number of times of erasing of a block including the plurality of memory cells connected to the word line; and when the calculated exhaustion degree is less than a predetermined threshold, perform a second threshold voltage tracking operation to cause the nonvolatile memory to determine an optimum read voltage, wherein, during the second threshold voltage tracking operation, the controller transmits to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line, wherein the nonvolatile memory is configured to, in response to the command, search an optimum read voltage for the plurality of memory cells connected to the word line using multiple read voltages, and to transmit a response including a search result. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the nonvolatile memory includes a plurality of blocks, each of which is a data erasure unit and includes word lines and memory cells connected to the word lines, and when receiving the transmitted response from the nonvolatile memory, the controller determines whether to store data stored in a first block including the plurality of memory cells connected to the word line, in a second block, based on the received response. ### Claim 3 (depends on 2) The memory system according to claim 2, wherein the controller is configured to calculate a first difference that is a difference between the optimum read voltage determined through the second threshold voltage tracking operation and a preset read voltage, and stores the data stored in the first block in the second block when the first difference is larger than a first value. ### Claim 4 (depends on 2) The memory system according to claim 2, wherein when the search result indicates that the optimum read voltage was not calculated, the controller performs the first threshold voltage tracking operation by transmitting multiple read requests to the nonvolatile memory, calculates a second difference that is a difference between the optimum read voltage determined through the first threshold voltage tracking operation by the controller and the preset read voltage, and saves the data stored in the first block in the second block when the second difference is larger than a predetermined second value. ### Claim 5 (depends on 4) The memory system according to claim 4, wherein when the search result indicates that the optimum read voltage was not calculated, the controller reads data from the plurality of memory cells connected to the word lines, and then when the read data cannot be decoded, the controller performs the first threshold voltage tracking operation by transmitting multiple read requests to the nonvolatile memory. ### Claim 6 (depends on 1) The memory system according to claim 1, wherein the memory system is connectable to a host device, when a read request is received from the host device connected to the memory system, the controller reads first data corresponding to the read request from the nonvolatile memory, decodes the first data, and then when decoding of the first data is successful, the controller transmits the decoded first data to the host device, when decoding of the first data fails, the controller transmits the command, reads second data corresponding to the read request from the nonvolatile memory using the optimum read voltage determined through the second threshold voltage tracking operation, decodes the second data, and then when decoding of the second data is successful, transmits the decoded second data to the host device. ### Claim 7 (depends on 6) The memory system according to claim 6, wherein the controller stores a read voltage used to read the first data, and updates the stored read voltage with the optimum read voltage determined through the second threshold voltage tracking operation. ### Claim 8 (depends on 7) The memory system according to claim 7, wherein when the search result indicates that a read voltage could not be calculated, the controller performs the first threshold voltage tracking operation by transmitting multiple read requests to the nonvolatile memory, reads the data corresponding to the read request from the nonvolatile memory using the optimum read voltage determined through the first threshold voltage tracking operation, decodes third data using the optimum read voltage determined through the first threshold voltage tracking operation by the controller, and then when decoding of the third data is successful, transmits the decoded third data to the host device. ### Claim 9 (depends on 1) The memory system according to claim 1, wherein the memory system is connectable to a host device, and the controller is configured to read data stored in the nonvolatile memory using a physical address in response to a read request from the host device, the physical address being mapped to a logical address specified by the read request. ### Claim 10 (depends on 1) The memory system according to claim 1, wherein the nonvolatile memory includes a plurality of blocks, each of which is a data erasure unit and includes word lines and memory cells connected to the word lines, and when receiving the transmitted response from the nonvolatile memory, the controller determines whether to store data stored in a first block including the plurality of memory cells connected to the word line, in a second block, based on the received response. ### Claim 11 (depends on 10) The memory system according to claim 10, wherein the controller is configured to calculate a first difference that is a difference between the optimum read voltage determined through the second threshold voltage tracking operation and a preset read voltage, and store the data stored in the first block in the second block when the first difference is larger than a first value. ### Claim 12 (depends on 10) The memory system according to claim 10, wherein when the search result indicates that the optimum read voltage was not calculated, the controller performs the first threshold voltage tracking operation by transmitting multiple read requests to the nonvolatile memory, calculates a second difference that is a difference between the optimum read voltage determined through the first threshold voltage tracking operation by the controller and the preset read voltage, and saves the data stored in the first block in the second block when the second difference is larger than a predetermined second value. ### Claim 13 (depends on 1) The memory system according to claim 1, wherein the command specifies a minimum voltage value and a change read voltage from a minimum voltage value, and the nonvolatile memory is configured to search the optimum read voltage using the minimum voltage value and the change read voltage. ### Claim 14 (depends on 1) The memory system according to claim 1, wherein the memory system is connectable to a host device, and the controller is configured to read data stored in the nonvolatile memory using a physical address in response to a read request from the host device, the physical address being mapped to a logical address specified by the read request.