# US 10,770,140 B2 · Memristive array with parallel reset control devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,140 B2 - Document ID: US10770140B2 - Status: Granted - Kind: B2 - Application number: 16/065,771 - Filed: 2016-01-27 - Published: 2019-01-24 - Granted: 2020-09-08 - Earliest claimed: 2016-01-27 - Assignees: Hewlett Packard Enterprise Development LP - Applicants: Hewlett Packard Enterprise Development LP - Inventors: John Paul Strachan; Brent Buchanan; Le Zheng - Web page: https://patentgrep.com/patent/US10770140B2 ## CPC - G11C 13/0069: {Writing or programming circuits or methods} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 13/003: {Cell access} - G11C 13/0097: {Erasing, e.g. resetting, circuits or methods} - G06F 2207/4814: Non-logic devices, e.g. operational amplifiers - G06F 2207/4828: Negative resistance devices, e.g. tunnel diodes, gunn effect devices - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 2213/79: Array wherein the access device being a transistor - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present disclosure provides a memristive array. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices. ## Claims ### Claim 1 A memristive array comprising: a number of memristive devices, wherein a memristive device is switchable between states and is to store information; and a parallel reset control device coupled to the number of memristive devices in parallel to regulate a resetting operation for the number of memristive devices by regulating current flow through target memristive devices, wherein the regulating of the resetting operation comprises drawing current away from a target memristive device as the target memristive device approaches a target state of the states between which the memristive device is switchable, wherein the parallel reset control device comprises multiple sets of fixed value resistors each being coupled in parallel to a respective set of memristive devices and wherein the parallel reset control device comprises a plurality of parallel reset controllers, each parallel reset controller comprising a set of fixed value resistors of the multiple sets of fixed value resistors, each parallel reset controller being coupled in parallel to a set of the number of memristive devices in a row of the memristive array. ### Claim 2 (depends on 1) The memristive array of claim 1, wherein regulating a resetting operation comprises placing the target memristive device in one of multiple states while going from a low resistance state to a high resistance state. ### Claim 3 (depends on 1) The memristive array of claim 1, wherein the memristive devices are multi-level memristors. ### Claim 4 (depends on 1) The memristive array of claim 1, wherein a selecting transistor is coupled to each memristive device of the number of memristive devices. ### Claim 5 (depends on 1) The memristive array of claim 1, wherein each fixed value resistor of each set of fixed value resistors is configured with a different resistance level. ### Claim 6 (depends on 5) The memristive array of claim 5, wherein drawing current away from a target memristive device as the target memristive device approaches a target state of the states between which the memristive device is switchable comprises activating a corresponding fixed value resistor of a set of fixed value resistors coupled in parallel to the target memristive devices, the corresponding fixed value resistor having a resistance level associated with the target state. ### Claim 7 A method for programming a memristive array comprising: selecting a target state for a target memristive device; setting a resistance of a parallel reset controller coupled to the target memristive device to a resistance value that corresponds to the target state, wherein the parallel reset controller comprises multiple sets of fixed value resistors each being coupled in parallel to a respective set of memristive devices comprising the target memristive device, and wherein the parallel reset controller is configured to regulate a resetting operation by drawing current away from a target memristive device as the target memristive device approaches the target state; programming a state of the target memristive device to the target state by: generating a voltage potential across the target memristive device by applying a first voltage to a row line corresponding to the target memristive device and a ground voltage to a first column line corresponding to the target memristive device; and generating a voltage potential across the parallel reset controller. ### Claim 8 (depends on 7) The method of claim 7, wherein setting a resistance of the parallel reset controller to a resistance value comprises activating one of a set of fixed value resistors of the parallel reset controller. ### Claim 9 (depends on 7) The method of claim 7, wherein drawing current away from a target memristive device as the target memristive device approaches the target state comprises placing the target memristive device in one of multiple states while going from a first resistance state to the target resistance state. ### Claim 10 A memristive crossbar array comprising: a number of row lines; a number of column lines intersecting the row lines to form a number of junctions; a number of memristive devices coupled between the row lines and the column lines at the junctions, wherein a memristive device is switchable between states to store information; multiple parallel reset controllers, a parallel reset controller coupled to a row line to regulate current through a corresponding row of memristive devices by drawing current away from a target memristive devices when a resistance of the target memristive device reaches a threshold value, the drawing including activating a corresponding fixed value resistor of a set of fixed value resistors coupled in parallel to the target memristive devices, the corresponding fixed value resistor having a resistance level associated with the target state, and wherein the parallel reset controllers each comprise multiple sets of fixed value resistors each being coupled in parallel to a respective row of a set of the number of memristive devices. ### Claim 11 (depends on 10) The memristive crossbar array of claim 10, further comprising a selecting transistor coupled to each of the memristive devices to regulate current flow through a corresponding memristive device. ### Claim 12 (depends on 10) The memristive crossbar array of claim 10, wherein the threshold value is one of a set of threshold values enforced by the parallel reset controller. ### Claim 13 (depends on 12) The memristive crossbar array of claim 12, wherein the resistance of each fixed value resistor defining a threshold value. ### Claim 14 (depends on 10) The memristive crossbar array of claim 10, further comprising a set controller to regulate the setting operation of a target memristive device. ### Claim 15 (depends on 10) The memristive crossbar array of claim 10, wherein a selecting transistor is coupled to each memristive device of the number of memristive devices. ### Claim 16 A method for programming a memristive array comprising: selecting a target state for a target memristive device; setting a resistance of a parallel reset controller coupled to the target memristive device to a resistance value that corresponds to the target state, wherein the parallel reset controller comprises multiple sets of fixed value resistors each being coupled in parallel to a respective set of memristive devices comprising the target memristive device, and wherein the parallel reset controller is configured to regulate a resetting operation by drawing current away from a target memristive device as the target memristive device approaches the target state; programming a state of the target memristive device to the target state by: generating a voltage potential across the target memristive device; and generating a voltage potential across the parallel reset controller by applying first voltage to a row line corresponding to the target memristive device and grounding a second column line corresponding to a fixed value resistor of the parallel reset controller.