# US 10,770,134 B2 · SRAM based authentication circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,134 B2 - Document ID: US10770134B2 - Status: Granted - Kind: B2 - Application number: 16/202,584 - Filed: 2018-11-28 - Published: 2019-03-28 - Granted: 2020-09-08 - Earliest claimed: 2016-10-07 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Chien-Chen Lin; Wei-Min Chan; Chih-Yu Lin; Shih-Lien Linus Lu; Yen-Huei Chen - Web page: https://patentgrep.com/patent/US10770134B2 ## CPC - G11C 11/419: Read-write [R-W] circuits - G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells - G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction - G11C 11/418: Address circuits - H04L 9/3278: {using physically unclonable functions [PUF]} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G11C: STATIC STORES (semiconductor memory devices H10B) - G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature. ## Claims ### Claim 1 A memory device, comprising: a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state; a physically unclonable function (PUF) generator, comprising: a first sense amplifier, coupled to the plurality of memory cells, wherein while at least some of the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, located in first and second columns of the memory cell array, respectively, and based on the comparison, provide a first output signal for generating a first PUF signature; and a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on a data state of the plurality of memory cells before the first and second memory cells are accessed. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first and second memory cells are arranged in a same row of the memory cell array and arranged in a first column and a second column of the memory cell array, respectively, and wherein the first and second columns are next to each other without additional column therebetween. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the first sense amplifier is coupled to a bit line of the first column and a bit line of the second column, and wherein the bit line of the first column is coupled to the first memory cell and the bit line of the second column is coupled to the second memory cell. ### Claim 4 (depends on 3) The memory device of claim 3, further comprising a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells. ### Claim 5 (depends on 4) The memory device of claim 4, wherein when the data state is a logical 0, the PC/PD circuit is configured to pre-charge the bit lines of the first and second columns to a positive supply voltage before the data states of the first and second memory cells are read. ### Claim 6 (depends on 5) The memory device of claim 5, wherein when the data state is a logical 1, the PC/PD circuit is configured to pre-discharge the bit lines of the first and second columns to ground before the data states of the first and second memory cells are read. ### Claim 7 (depends on 5) The memory device of claim 5, wherein during the data states of the first and second memory cells are being read, the first and second cells are supplied with a voltage level that is lower than the positive supply voltage. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the PUF generator further comprises: a second sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being read by respective sense amplifiers different from the second sense amplifier, the second sense amplifier is configured to compare either respective discharging rates or respective charging rates of third and fourth memory cells of the plurality of memory cells that are adjacent to each other, and based on the comparison, provide a second output signal for generating the first PUF signature. ### Claim 9 A memory device, comprising: a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state; a physically unclonable function (PUF) generator, comprising: a first sense amplifier, coupled to first and second memory cells of the plurality of memory cells, and a second sense amplifier, also coupled to the first and second memory cells of the plurality of memory cells, wherein the first and second memory cells are located in first and second columns of the memory cell array, respectively; and a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on a data state of the plurality of memory cells before the first and second memory cells are accessed. ### Claim 10 (depends on 9) The memory device of claim 9, wherein while the data states of the plurality of memory cells are being read by respective sense amplifiers different from the first and second sense amplifiers, the first sense amplifier is configured to compare respective discharging rates of the first and second memory cells, the second sense amplifier is configured to compare respective charging rates of the first and second memory cells, and based on a first voltage difference according to the comparison on the discharging rates, the first amplifier is configured to provide a first output signal and based on a second voltage difference according to the comparison on the charging rates, the second sense amplifier is configured to provide a second output signal, and wherein the first and second output signals are used for generating a PUF signature, and wherein the first sense amplifier is coupled to a bit line of a first column and a bit line of a second column, wherein the second sense amplifier is coupled to a bit bar line of the first column and a bit bar line of the second column, and wherein the bit line and the bit bar line of the first column is coupled to the first memory cell and the bit line and the bit bar line of the second column is coupled to the second memory cell. ### Claim 11 (depends on 10) The memory device of claim 10, wherein the first and second memory cells are arranged in a same row of the memory cell array and arranged in the first column and the second column of the memory cell array, respectively, and wherein the first and second columns are next to each other without an additional column therebetween. ### Claim 12 (depends on 10) The memory device of claim 10, wherein when the data state is a logical 0, the PC/PD circuit is configured to pre-charge the bit lines of the first and second columns to a positive supply voltage before the data states of the first and second memory cells are read, and pre-discharge the bit bar lines of the first and second columns to ground before the data states of the first and second memory cells are read. ### Claim 13 (depends on 10) The memory device of claim 10, wherein when the data state is a logical 1, the PC/PD circuit is configured to pre-discharge the bit lines of the first and second columns to ground before the data states of the first and second memory cells are read, and pre-charge the bit bar lines of the first and second columns to the positive supply voltage before the data states of the first and second memory cells are read. ### Claim 14 (depends on 10) The memory device of claim 10, wherein during the data states of the first and second memory cells are being read, the first and second cells are supplied with a voltage level that is lower than positive supply voltage. ### Claim 15 A memory device, comprising: a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state; a physically unclonable function (PUF) generator, coupled to the plurality of memory cells, that comprises: a first sense amplifier, and a column decoder, coupled between the plurality of memory cells and the first sense amplifier, that comprises at least four switches wherein each of the switches is coupled to one of four columns of the memory cell array, wherein while the data states of the plurality of memory cells are being read, the column decoder is configured to assert two of the four switches so as to allow the first sense amplifier to compare either respective discharging rates or respective charging rates of first and second memory cells of the plurality of memory cells that are coupled to the first sense amplifier through the asserted switches, and based on a voltage difference according to the comparison, provide an output signal for generating a PUF signature, wherein the first and second memory cells are located in first and second columns of the memory cell array, respectively; and a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on the data state of the plurality of memory cells before the first and second memory cells are accessed. ### Claim 16 (depends on 15) The memory device of claim 15, wherein each column of the memory cell array includes a bit line and a bit bar line, and the switch of the column decoder is coupled to either a bit line or a bit bar line of one of the columns of the memory cell array. ### Claim 17 (depends on 15) The memory device of claim 15, wherein during the data states of the first and second memory cells being read, the first and second cells are supplied with a voltage level that is lower than a positive supply voltage. ### Claim 18 (depends on 15) The memory device of claim 15, wherein the first and second memory cells are arranged in a same row of the memory cell array and arranged in the first column and the second column of the memory cell array, respectively, and wherein the first and second columns are next to each other without an additional column therebetween. ### Claim 19 (depends on 15) The memory device of claim 15, wherein when the data state is a logical 0, the PC/PD circuit is configured to pre-charge the bit lines of the first and second columns to a positive supply voltage before the data states of the first and second memory cells are read, and pre-discharge the bit bar lines of the first and second columns to ground before the data states of the first and second memory cells are read. ### Claim 20 (depends on 15) The memory device of claim 15, wherein when the data state is a logical 1, the PC/PD circuit is configured to pre-discharge the bit lines of the first and second columns to ground before the data states of the first and second memory cells are read, and pre-charge the bit bar lines of the first and second columns to the positive supply voltage before the data states of the first and second memory cells are read.