# US 10,770,133 B1 · Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits

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- Number: US 10,770,133 B1
- Document ID: US10770133B1
- Status: Granted
- Kind: B1
- Application number: 16/111,182
- Filed: 2018-08-23
- Granted: 2020-09-08
- Earliest claimed: 2016-12-06
- Applicants: GSI Technology, Inc.
- Inventors: Bob Haig; Eli Ehrman; Patrick Chuang; Chao-Hung Chang; Mu-Hsiang Huang
- Web page: https://patentgrep.com/patent/US10770133B1

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/418: Address circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bl-sects for an extended period of time, to save power.

## Claims

### Claim 1

A processing array device, comprising:
a plurality of memory cells arranged in an array having a plurality of columns and a plurality of rows, each memory cell having a storage element wherein the array has a plurality of sections and each section has a plurality of bit line sections and a plurality of bit lines with one bit line per bit line section, wherein the memory cells in each bit line section are all connected to a single read bit line and the plurality of bit lines in each section are distinct from the plurality of bit lines included in the other sections of the array; and
wherein each bit line section further comprises a write inhibit circuitry that inhibits a write operation to the memory cells of the bit line section on a per write operation basis, a pullup element connected to the read bit line to pre-charge the read bit line to a logic “1”, and a pre-charge inhibit circuitry that inhibits the pre-charge of the read bit line for a period of time.

### Claim 2 (depends on 1)

The processing array of claim 1, wherein the write inhibit circuitry inhibits the write operation of the memory cells of the bit line section when the pre-charge of the read bit line is inhibited for the same period of time.

### Claim 3 (depends on 1)

The processing array of claim 1, wherein the write inhibit circuitry further comprises a first AND logic gate that generates a state of a positive write bit line based on a write enable signal and a write data signal and a second AND logic gate that generates a state of a negative write bit line based on the write enable signal and the write data signal.

### Claim 4 (depends on 1)

The processing array of claim 1 further comprising a read circuitry, in each bit line section, that receives read data from the single read bit line of the bit line section, a write circuitry, in each bit line section, that receives read data output from a plurality of adjacent bit line sections in the processing array and outputs selected write data to be written to the one or more of the memory cells in the bit line section, a GRE control signal that, when asserted, indicates that an active read operation to the one or more memory cells in the bit line section is in progress and a GWE control signal that, when asserted, indicates that an active write operation to the one or more memory cells is in progress.

### Claim 5 (depends on 4)

The processing array of claim 4 further comprising a “write if valid” control signal that is asserted to de-assert the write enable signal, if the state of a e WMUX output is “0”, and inhibit a write operation in the bit line section for a particular write operation.

### Claim 6 (depends on 5)

The processing array of claim 5, wherein the write enable signal is asserted when the GWE signal is asserted.

### Claim 7 (depends on 6)

The processing array of claim 6 further comprising a first logic gate that generates a write inhibit signal and a second logic gate that receives the write inhibit signal and an inverted GWE signal and generates the write enable signal.

### Claim 8 (depends on 1)

The processing array of claim 1, wherein the pre-charge inhibit circuitry further comprises a pulldown element connected to the read bit line and a latch, when set, that indicates that the bit line section is decommissioned, the latch having a set input that is asserted when an inhibit set control signal is asserted and a state of the read bit line is “0” and reset input that is asserted when an inhibit reset signal is asserted.

### Claim 9 (depends on 8)

The processing array of claim 8, wherein the pulldown element is disabled when the latch is in a reset state.

### Claim 10 (depends on 9)

The processing array of claim 9, wherein the pulldown element is enabled and the pullup element is disabled when the latch is in a set state, that disables the pre-charge of the read bit line until the bit line section is not decommissioned.

### Claim 11 (depends on 10)

The processing array of claim 10, wherein a The positive write bit line and a negative write bit line are active when the latch is in a reset state.

### Claim 12 (depends on 11)

The processing array of claim 11, wherein a positive write bit line and a negative write bit line are inhibited when the latch is in a set state.

### Claim 13

A method, comprising:
providing a plurality of memory cells arranged in an array having a plurality of columns and a plurality of rows, each memory cell having a storage element wherein the array has a plurality of sections and each section has a plurality of bit line sections and a plurality of bit lines with one bit line per bit line section, wherein the memory cells in each bit line section are all connected to a single read bit line and the plurality of bit lines in each section are distinct from the plurality of bit lines included in the other sections of the array;
inhibiting, by a write inhibit circuitry, a write operation to the memory cells of the bit line section on a per write operation basis;
precharging, by pullup element connected to the read bit line, the read bit line to a logic “1”; and
inhibiting, by a pre-charge inhibit circuitry, the pre-charge of the read bit line for a period of time.

### Claim 14 (depends on 13)

The method of claim 13, wherein inhibiting the write operation of the memory cells of the bit line section further comprises inhibiting the write operation of the memory cells of the bit line section when the pre-charge of the read bit line is inhibited for the same period of time.

### Claim 15 (depends on 14)

The method array of claim 14, wherein inhibiting the write operation of the memory cells of the bit line section further comprising generating, by a first AND logic gate, a state of a positive write bit line based on a write enable signal and a write data signal and generating, by a second AND logic gate, a state of a negative write bit line based on the write enable signal and the write data signal.

### Claim 16 (depends on 13)

The method of claim 13 further comprising generating a GRE control signal that, when asserted, indicates that an active read operation to the one or more memory cells in the bit line section is in progress and generating a GWE control signal that, when asserted, indicates that an active write operation to the one or more memory cells is in progress.

### Claim 17 (depends on 16)

The method of claim 16 further comprising asserting a “write if valid” control signal to de-assert the write enable signal and inhibit a write operation in the bit line section for a particular write operation.

### Claim 18 (depends on 17)

The method of claim 17 further comprising asserting the write enable signal when the GWE signal is asserted.

### Claim 19 (depends on 18)

The method of claim 18 further comprising generating a write inhibit signal and generating the write enable signal based on the write inhibit signal and an inverted GWE signal.

### Claim 20 (depends on 13)

The method of claim 13, wherein inhibiting the pre-charge further comprises setting a latch that indicates that the bit line section is decommissioned, the latch having a set input that is asserted when an inhibit set control signal is asserted and a state of the read bit line is “0” and reset input that is asserted when an inhibit reset signal is asserted.

### Claim 21 (depends on 20)

The method of claim 20 further comprising disabling a pulldown element when the inhibit set control signal is not asserted.

### Claim 22 (depends on 21)

The method of claim 21 further comprising enabling the pulldown element when the inhibit set control signal is asserted that disables the pre-charge of the read bit line until the bit line section is not decommissioned.

### Claim 23 (depends on 22)

The method of claim 22 further comprising activating a positive write bit line and a negative write bit line when the inhibit set control signal is not asserted.

### Claim 24 (depends on 23)

The method of claim 23 further comprising inhibiting the positive write bit line and the negative write bit line when the inhibit set control signal is asserted.