# US 10,770,130 B2 · Apparatuses and methods for maintaining a duty cycle error counter

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- Number: US 10,770,130 B2
- Document ID: US10770130B2
- Status: Granted
- Kind: B2
- Application number: 16/557,933
- Filed: 2019-08-30
- Published: 2020-01-02
- Granted: 2020-09-08
- Earliest claimed: 2018-01-11
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yasuo Satoh; Tyler J. Gomm
- Web page: https://patentgrep.com/patent/US10770130B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015})
- H03K 5/1565: {the output pulses having a constant duty cycle}
- H03K 23/005: {using minimum change code, e.g. Gray Code}
- H03M 7/16: Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

## Claims

### Claim 1

An apparatus comprising:
a counter, wherein the counter is configured to:
encode a first value to a second value, wherein the first value is represented by a binary code and the second value is represented by a Gray code,
count up or count down the second value by a specified step to output a third value, wherein the third value is represented by the Gray code, and
decode the third value to a fourth value, wherein the fourth value is represented by the binary code.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein to encode the first value to the second value comprises using bitwise XOR logic to compare binary code bit values and Gray code bit values.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein to decode the third value to the fourth value comprises using bitwise XOR logic to compare binary code bit values.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein to count up or count down the second value by the specified step to output the third value is in response to a clock signal and based on an UP/DOWN signal, wherein the UP/DOWN signal indicates an increment or decrement of the counter.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the specified step is greater than a one bit step.

### Claim 6

An apparatus comprising:
a duty cycle detect circuit configured to store a duty cycle error count value associated with a clock signal using a first code, wherein the duty cycle detect circuit is further configured to convert the duty cycle error count value from the first code to a second code to provide as an output count value; and
a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the output count value.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the duty cycle detect circuit is configured to adjust the duty cycle error count value in response to detection of a duty cycle error of the clock signal.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the first code is Gray code and the second code is binary code.

### Claim 9 (depends on 6)

The apparatus of claim 6, wherein the duty cycle detect circuit comprises a counter to store the duty cycle error count value.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the counter includes a bit cell configured to store a bit of the duty cycle error count value.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the bit cell is further configured to a next value of the bit in the first code based on a current value of the bit in the second code and a bit value in the second code from a next higher order bit cell.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the bit cell is configured to use XOR logic to compare the current value of the bit in the second code and a bit value in the second code from a next higher order bit cell to determine the next value of the bit in the first code.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the bit cell comprises a flip-flop circuit configured to set the bit to the next value in the second code in response to an adjustment clock signal.

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein the bit cell is configured to determine the current bit value in the second code included in the output count value based on the bit in the second code and a bit from a next higher order bit cell in the first code.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the bit cell is configured to use XOR logic to compare the bit in the second code and the bit from the next higher order bit cell in the first code to determine the current binary bit value included in the output count value.

### Claim 16

A method comprising:
storing a count value indicating a duty cycle error of a clock signal using a first code;
converting the count value from the first code to a second code to provide an output count value; and
providing a duty cycle error signal based on the output count value.

### Claim 17 (depends on 16)

The method of claim 16, further comprising adjusting a duty cycle of the clock signal based on the duty cycle error signal.

### Claim 18 (depends on 16)

The method of claim 16, further comprising, in response to detecting a duty cycle error, adjusting the count value.

### Claim 19 (depends on 18)

The method of claim 18, further comprising comparing a current value of a bit of the count value in the second code with a next state bit value in the second code from a next higher order bit of the count value to adjust the bit of the count value.

### Claim 20 (depends on 19)

The method of claim 19, further comprising using XOR logic to perform the comparison between the current value of the bit of the count value in the second code with the next state bit value in the second code from the next higher order bit of the count value.