# US 10,770,129 B2 · Pseudo-channeled DRAM

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- Number: US 10,770,129 B2
- Document ID: US10770129B2
- Status: Granted
- Kind: B2
- Application number: 16/106,911
- Filed: 2018-08-21
- Published: 2019-02-07
- Granted: 2020-09-08
- Earliest claimed: 2018-08-21
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Hussein Alameer; Kjersten Criss; Uksong Kang
- Web page: https://patentgrep.com/patent/US10770129B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- H10D 89/10: Integrated device layouts
- G11C 2207/105: Aspects related to pads, pins or terminals
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.

## Claims

### Claim 1

A memory system, comprising:
two or more dynamic random access memory devices; and
logic communicatively coupled to the two or more dynamic random access memory devices to:
provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel;
dedicate data pins for each of the pseudo-channels; and
share command address pins between at least two of the two or more pseudo-channels.

### Claim 2 (depends on 1)

The system of claim 1, wherein the logic is further to:
share data strobe pins between at least two of the two or more pseudo-channels.

### Claim 3 (depends on 2)

The system of claim 2, wherein the logic is further to:
provide single device data correction for the two or more dynamic random access memory devices.

### Claim 4 (depends on 1)

The system of claim 1, wherein the logic is further to:
provide double data rate data transfer.

### Claim 5 (depends on 1)

The system of claim 1, wherein each of the two or more dynamic random access memory devices has a four bit data width.

### Claim 6 (depends on 1)

The system of claim 1, wherein each of the two or more dynamic random access memory devices has an eight bit data width.

### Claim 7 (depends on 1)

The system of claim 1, wherein the two or more dynamic random access memory devices are mounted on a dual-inline memory module.

### Claim 8

A semiconductor apparatus, comprising:
one or more substrates;
dynamic random access memory coupled to the one or more substrates; and
logic coupled to the one or more substrates and the dynamic random access memory, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
layout the dynamic random access memory with two or more pseudo-channels per memory channel; and
dedicate data pins for each of the pseudo-channels.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the logic is further to:
share command address pins between at least two of the two or more pseudo-channels.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the logic is further to:
share data strobe pins between at least two of the two or more pseudo-channels.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the logic is further to:
provide single device data correction for the dynamic random access memory.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the logic is further to:
provide double data rate data transfer.

### Claim 13 (depends on 8)

The apparatus of claim 8, wherein the dynamic random access memory has a four bit data width.

### Claim 14 (depends on 8)

The apparatus of claim 8, wherein the dynamic random access memory has an eight bit data width.

### Claim 15 (depends on 8)

The apparatus of claim 8, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

### Claim 16

A method of organizing memory, comprising:
providing two or more dynamic random access memory devices; and
providing access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel; and
sharing command address pins between at least two of the two or more pseudo-channels.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
dedicating data pins for each of the pseudo-channels.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
sharing data strobe pins between at least two of the two or more pseudo-channels.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
providing single device data correction for the two or more dynamic random access memory devices.