# US 10,770,124 B2 · Memory device comprising programmable command-and-address and/or data interfaces > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,124 B2 - Document ID: US10770124B2 - Status: Granted - Kind: B2 - Application number: 16/222,909 - Filed: 2018-12-17 - Published: 2019-07-04 - Granted: 2020-09-08 - Earliest claimed: 2012-01-30 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Ian Shaeffer; Lawrence Lai; Fan Ho; David A. Secker; Wayne S. Richardson; Akash Bansal; Brian S. Leibowitz; Kyung Suk Oh - Web page: https://patentgrep.com/patent/US10770124B2 ## CPC - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating} - G11C 7/1045: {Read-write mode select circuits} - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - H10W 90/00: Package configurations - H10W 72/07554: {changes in dispositions} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5366: {the bond wires having kinks} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/547: {Dispositions of multiple bond wires} - H10W 72/551: {Materials of bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. ## Claims ### Claim 1 A first memory device, comprising: a first set of pins symmetrically arranged on both sides of a first line of symmetry, wherein the first set of pins is suitably arranged for use in a clamshell configuration; a first command-and-address (CA) interface to receive command and address information, the first CA interface including a first subset of the first set of pins located on a first side of the first line of symmetry; and a set of data interfaces including a respective second subset of the first set of pins, wherein a variable number of data interfaces of the set of data interfaces are active in accordance with a plurality of selectable operation modes. ### Claim 2 (depends on 1) The first memory device of claim 1, wherein the first set of pins are arranged in a plurality of rows of pins that are parallel to the first line of symmetry, and wherein each row of pins on one side of the first line of symmetry mirrors a respective row of pins on an opposite side of the first line of symmetry. ### Claim 3 (depends on 1) The first memory device of claim 1, comprising a second CA interface to receive command and address information, the second CA interface including a third subset of the first set of pins located on a second side of the first line of symmetry that is opposite of the first side. ### Claim 4 (depends on 3) The first memory device of claim 3, wherein the first subset of the first set of pins and the third subset of the first set of pins are equidistant from the first line of symmetry. ### Claim 5 (depends on 3) The first memory device of claim 3, wherein the first CA interface and the second CA interface are selectable, to receive command and address information, based on information stored in one or more registers. ### Claim 6 (depends on 3) The first memory device of claim 3, wherein the first CA interface and the second CA interface are independent of each other. ### Claim 7 (depends on 1) The first memory device of claim 1, wherein an operation mode is selected from the plurality of selectable operation modes based on a signal received at a pin in the first set of pins. ### Claim 8 (depends on 1) The first memory device of claim 1, wherein the first memory device and a second memory device are disposed facing each other on a circuit board, wherein the second memory device comprises a second set of pins symmetrically arranged on both sides of a second line of symmetry, and wherein pins of the first memory device located on one side of the first line of symmetry face pins of the second memory device located on a respective opposite side of the second line of symmetry. ### Claim 9 A first memory device, comprising: a first set of pins arranged on a first surface of the first memory device wherein the first set of pins is suitably arranged for use in a clamshell configuration; a first command-and-address (CA) interface including a first subset of the first set of pins; a second CA interface including a second subset of the first set of pins; wherein the first subset of the first set of pins and the second subset of the first set of pins are located on opposite sides of a first line on the first surface; and a set of data interfaces including a third subset of the first set of pins, wherein a variable number of data interfaces of the set of data interfaces are active in accordance with a plurality of selectable operation modes. ### Claim 10 (depends on 9) The first memory device of claim 9, wherein the first set of pins are arranged in a plurality of rows of pins that are parallel to the first line, and wherein each row of pins on one side of the first line mirrors a respective row of pins on an opposite side of the first line. ### Claim 11 (depends on 9) The first memory device of claim 9, wherein the first subset of the first set of pins and the second subset of the first set of pins are equidistant from the first line. ### Claim 12 (depends on 9) The first memory device of claim 9, wherein the first CA interface and the second CA interface are selectable, to receive command and address information, based on information stored in one or more registers. ### Claim 13 (depends on 9) The first memory device of claim 9, wherein the first CA interface and the second CA interface are independent of each other. ### Claim 14 (depends on 9) The first memory device of claim 9, wherein an operation mode is selected from the plurality of selectable operation modes based on a signal received at a pin in the first set of pins. ### Claim 15 (depends on 9) The first memory device of claim 9, wherein the first memory device and a second memory device are disposed on a circuit board so that the first surface of the first memory device faces a second surface of the second memory device, wherein the second memory device comprises (1) a second set of pins arranged on the second surface, (2) a third CA interface including a first subset of the second set of pins, wherein the third CA interface corresponds to the first CA interface, and (3) a fourth CA interface including a second subset of the second set of pins, wherein the fourth CA interface corresponds to the second CA interface, and wherein the first subset of the first set of pins faces the second subset of the second set of pins, and the second subset of the first set of pins faces the first subset of the second set of pins. ### Claim 16 A method, comprising: in a memory device having (1) a set of pins symmetrically arranged on both sides of a line of symmetry, wherein the set of pins is suitably arranged for use in a clamshell configuration, (2) a first command-and-address (CA) interface including a first subset of the set of pins located on a first side of the line of symmetry, and (3) a set of data interfaces including a second subset of the set of pins, wherein a variable number of data interfaces of the set of data interfaces are active in accordance with a plurality of selectable operation modes, receiving command and address information via the first subset of the set of pins, and communicating data via the second subset of the set of pins. ### Claim 17 (depends on 16) The method of claim 16, wherein the memory device comprises a second CA interface including a third subset of the set of pins located on a second side of the line of symmetry that is opposite to the first side, and wherein the method comprising selecting the first CA interface to receive command and address information based on information stored in one or more registers. ### Claim 18 (depends on 16) The method of claim 16, comprising: receiving a signal at a pin in the set of pins; and selecting an operation mode of the plurality of selectable operation modes based on the signal.