# US 10,770,120 B2 · Memory system and operating method of the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,120 B2 - Document ID: US10770120B2 - Status: Granted - Kind: B2 - Application number: 16/109,169 - Filed: 2018-08-22 - Published: 2019-08-15 - Granted: 2020-09-08 - Earliest claimed: 2018-02-09 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Byung-Jun Kim - Web page: https://patentgrep.com/patent/US10770120B2 ## CPC - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 5/144: {Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby} - G11C 16/225: {Preventing erasure, programming or reading when power supply voltages are outside the required ranges} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A memory system includes: a sudden power off (SPO) frequency value calculator suitable for determining a SPO frequency value; a checkpointing mode controller suitable for setting the memory system to one among a high frequency checkpointing mode and a low frequency checkpointing mode according to the SPO frequency value; and a processor suitable for performing a checkpointing operation according to the set frequency checkpointing mode. ## Claims ### Claim 1 A memory system comprising: a sudden power off (SPO) frequency value calculator suitable for determining a SPO frequency value; a checkpointing mode controller suitable for setting the memory system to one among a high frequency checkpointing mode and a low frequency checkpointing mode according to the SPO frequency value; and a processor suitable for performing a checkpointing operation according to the set frequency checkpointing mode. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the checkpointing mode controller compares the SPO frequency value with a SPO frequency threshold value. ### Claim 3 (depends on 2) The memory system of claim 2, wherein the SPO frequency value calculator determines the SPO frequency value through a current value and a weighted value of respective calculation factors. ### Claim 4 (depends on 2) The memory system of claim 2, wherein the SPO frequency value calculator determines the SPO frequency threshold value through a threshold value and a weighted value of respective calculation factors. ### Claim 5 (depends on 2) The memory system of claim 2, wherein the checkpointing mode controller sets the memory system to the high frequency checkpointing mode when the SPO frequency value is greater than or equal to the SPO frequency threshold value. ### Claim 6 (depends on 2) The memory system of claim 2, wherein the checkpointing mode controller sets the memory system to the low frequency checkpointing mode when the SPO frequency value is less than the SPO frequency threshold value. ### Claim 7 (depends on 3) The memory system of claim 3, wherein the calculation factors include at least one of a user type, a memory device type, and a count of recently occurred SPOs. ### Claim 8 An operating method of a memory system, the method comprising: determining, by a sudden power off (SPO) frequency value calculator, a SPO frequency value; setting, by a checkpointing mode controller, the memory system to one among a high frequency checkpointing mode and a low frequency checkpointing mode according to the SPO frequency value; and performing, by a processor, a checkpointing operation according to the set frequency checkpointing mode. ### Claim 9 (depends on 8) The method of claim 8, further comprising comparing the SPO frequency value with a SPO frequency threshold value. ### Claim 10 (depends on 9) The method of claim 9, wherein the determining of the SPO frequency value is performed through a current value and a weighted value of respective calculation factors. ### Claim 11 (depends on 9) The method of claim 9, wherein the determining of the SPO frequency value is performed through a threshold value and a weighted value of respective calculation factors. ### Claim 12 (depends on 9) The method of claim 9, wherein the setting of the memory system includes setting the memory system to the high frequency checkpointing mode when the SPO frequency value is greater than or equal to the SPO frequency threshold value. ### Claim 13 (depends on 9) The method of claim 9, wherein the setting of the memory system includes setting the memory system to the low frequency checkpointing mode when the SPO frequency value is less than the SPO frequency threshold value. ### Claim 14 (depends on 10) The method of claim 10, wherein the calculation factors include at least one of a user type, a memory device type, and a count of recently occurred SPOs. ### Claim 15 A memory system, comprising: a memory device; and a controller suitable for determining an operation mode of the memory system based on an occurrence number of sudden power offs (SPOs) and a type of the memory device, and backing up information required to boot based on the determined operation mode. ### Claim 16 (depends on 15) The memory system of claim 15, wherein the controller comprises: a SPO frequency value calculator suitable for determining a SPO frequency value as the occurrence number of SPOs based on the occurrence number of SPOs and the type of the memory device; a mode controller suitable for selecting one mode of a high frequency mode and a low frequency mode based on the determined SPO frequency value, and determining the selected one mode as the operation mode; and a processor suitable for backing up the information based on the operation mode. ### Claim 17 (depends on 16) The memory system of claim 16, wherein the mode controller compares the SPO frequency value with a threshold value, and selects one of both the high frequency mode and the low frequency mode based on the comparison result as the operation mode. ### Claim 18 (depends on 17) The memory system of claim 17, wherein the mode controller selects the high frequency mode to increase a current frequency for the backing up of the information when the SPO frequency value is greater than or equal to the threshold value. ### Claim 19 (depends on 17) The memory system of claim 17, wherein the mode controller selects the low frequency mode to decrease a current frequency for the backing up of the information when the SPO frequency value is less than the threshold value.