# US 10,770,100 B1 · Balanced current mirrors for biasing a magnetic resistor in a hard disk drive > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,100 B1 - Document ID: US10770100B1 - Status: Granted - Kind: B1 - Application number: 16/702,983 - Filed: 2019-12-04 - Granted: 2020-09-08 - Earliest claimed: 2018-12-05 - Assignees: Marvell Asia Pte Ltd - Applicants: Marvell International Ltd. - Inventors: Xiaowei Huang; Mei Lei; Yunfan Zhang; Su Win Myat - Web page: https://patentgrep.com/patent/US10770100B1 ## CPC - G11B 5/3932: {Magnetic biasing films} - G05F 3/262: {using field-effect transistors only} - G11B 5/012: Recording on, or reproducing or erasing from, magnetic disks (G11B17/00, G11B19/00 take precedence) - G11B 5/02: Recording, reproducing, or erasing methods; Read, write or erase circuits therefor - G11B 2005/0018: {by current biasing control or regulation} - G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A bias circuit comprises a closed loop gain stage arranged to determine a difference between a first current in a first branch circuit and a second current in a second branch circuit, where the first branch circuit and second branch circuit are coupled to respective terminals of a magnetic resistor (MR). A first set of current mirrors is arranged to provide a source current to the first terminal of the MR and the second set of current mirrors is arranged to provide a sink current to the second terminal of the MR. The first set of current mirrors and a second set of current mirrors are balanced to reduce a difference in setting time between the source current and sink current. The source current and sink current further reduce the difference between the first current and the second current to provide a constant voltage bias to the MR based on a voltage of a voltage source. ## Claims ### Claim 1 A bias circuit comprising: a closed loop gain stage arranged to determine a difference between a first current in a first branch circuit and a second current in a second branch circuit, wherein the first branch circuit and the second branch circuit are coupled to respective terminals of a magnetic resistor (MR); and a first set of current mirrors and a second set of current mirrors which are balanced, the first set of current mirrors arranged to provide a source current to one of the terminals of the MR and the second set of current mirrors arranged to provide a sink current to another of the terminals of the MR to reduce the difference between the first current and the second current and provide a constant voltage bias to the MR based on a voltage of a voltage source. ### Claim 2 (depends on 1) The bias circuit of claim 1, wherein the first set of current mirrors comprises a current source mirror which sources the source current to the MR and the second set of current mirrors comprises a current sink mirror which sinks the sink current from the MR. ### Claim 3 (depends on 1) The bias circuit of claim 1, wherein each set of current mirrors have a same number of current mirrors. ### Claim 4 (depends on 1) The bias circuit of claim 1, wherein when the difference between the first current and the second current is less than a threshold amount, a voltage across the terminals of the MR is equal to the voltage of the voltage source. ### Claim 5 (depends on 1) The bias circuit of claim 1, further comprising a switch for providing the source current to the other of the terminal of the MR and the sink current to the one of the terminals of the MR. ### Claim 6 (depends on 1) The bias circuit of claim 1, further comprising a current driver which provides a reference current to the first set of current mirrors and to the second set of current mirrors. ### Claim 7 (depends on 6) The bias circuit of claim 6, further comprising a capacitor coupled between a gate of a transistor of the current driver and a voltage reference. ### Claim 8 (depends on 1) The bias circuit of claim 1, wherein the first set of current mirrors comprises a first NMOS (N-type metal oxide semiconductor) transistor and second NMOS transistor of a first current mirror and a third PMOS (P-type metal oxide semiconductor) transistor and fourth PMOS transistor of a second current mirror. ### Claim 9 (depends on 1) The bias circuit of claim 1, wherein the second set of current mirrors comprises a first PMOS transistor and second PMOS transistor of a first current mirror and a third NMOS transistor and fourth NMOS transistor of a second current mirror. ### Claim 10 (depends on 1) The bias circuit of claim 1, wherein a settling time of the source current and a settling time of the sink current are substantially equal. ### Claim 11 A method comprising: determining a difference between a first current in a first branch circuit and a second current in a second branch circuit, wherein the first branch circuit and the second branch circuit are coupled to respective terminals of a magnetic resistor (MR); outputting a reference current based on the difference; and performing a balanced mirroring of the reference current by a first set of current mirrors mirroring the reference current to provide a source current to one of the terminals and a second set of current mirrors mirroring the reference current to provide a sink current to another of the terminals, the source current and the sink current reducing the difference between the first current and the second current to provide a constant voltage bias to the MR based on a voltage of a voltage source. ### Claim 12 (depends on 11) The method of claim 11, wherein the first set of current mirrors mirroring the reference current comprises mirroring the reference current by a current sink mirror which sinks the sink current from the MR. ### Claim 13 (depends on 12) The method of claim 12, wherein the current sink mirror inverts a direction of the reference current which is mirrored. ### Claim 14 (depends on 11) The method of claim 11, wherein the second set of current mirrors mirroring the reference current comprises mirroring the reference current by a current source mirror which sources the source current to the MR. ### Claim 15 (depends on 11) The method of claim 11, where a settling time of the source current and the sink current are substantially equal. ### Claim 16 (depends on 11) The method of claim 11, wherein the first set of current mirrors and the second set of current mirrors each comprise two current mirrors. ### Claim 17 (depends on 11) The method of claim 11, further comprising determining data stored on a magnetic disk based on a resistance of the MR. ### Claim 18 A bias circuit comprising: a first branch comprising a first resistor and a first transistor, wherein one terminal of the first resistor is coupled to a collector of the first transistor, another terminal of the first resistor is coupled to a voltage reference, and an emitter of the first transistor is coupled to one terminal of an MR; a second branch comprising a second resistor and a second transistor, wherein one terminal of the second resistor is coupled to a collector of the second transistor, another terminal of the second resistor is coupled to the voltage reference, and an emitter of the second transistor is coupled to another terminal of the MR; a closed loop gain stage comprising a transimpedance amplifier (TIA) with one input coupled to the one terminal of the first resistor and another input coupled to the one terminal of the second resistor and an input of an error amplifier (EA) coupled to an output of the TIA; a current driver coupled to an output of the EA; and a first set of current mirrors coupled to the current driver and the one terminal of the MR and a second set of current mirrors coupled to the current driver and the other terminal of the MR, wherein each set of current mirrors have a same number of current mirrors. ### Claim 19 (depends on 18) The bias circuit of claim 18, wherein the first set of current mirrors comprises a first NMOS (N-type metal oxide semiconductor) transistor and second NMOS transistor of a first current mirror and a third PMOS (P-type metal oxide semiconductor) transistor and fourth PMOS transistor of second current mirror. ### Claim 20 (depends on 19) The bias circuit of claim 19, wherein the second set of current mirrors comprises a third PMOS transistor and fourth PMOS transistor of a third current mirror and a fifth NMOS transistor and sixth NMOS transistor of a fourth current mirror.