# US 10,770,086 B2 · Zero-latency pulse density modulation interface with format detection

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- Number: US 10,770,086 B2
- Document ID: US10770086B2
- Status: Granted
- Kind: B2
- Application number: 16/170,524
- Filed: 2018-10-25
- Published: 2019-08-22
- Granted: 2020-09-08
- Earliest claimed: 2018-02-19
- Assignees: Cirrus Logic, Inc.
- Applicants: Cirrus Logic International Semiconductor Ltd.
- Inventors: Masoud Farshbaf Zinati; Arun Ramani; Amar Vellanki; Xiaofan Fei
- Web page: https://patentgrep.com/patent/US10770086B2

## CPC

- G10L 19/032: Quantisation or dequantisation of spectral components
- G10L 19/005: Correction of errors induced by the transmission channel, if related to the coding algorithm
- G10L 19/008: Multichannel audio signal coding or decoding using interchannel correlation to reduce redundancy, e.g. joint-stereo, intensity-coding or matrixing
- G10L 19/26: Pre-filtering or post-filtering
- H03F 3/183: with semiconductor devices only
- H03F 3/217: Class D power amplifiers; Switching amplifiers
- H03F 3/2171: {with field-effect devices (H03F3/2173 - H03F3/2178 take precedence)}
- H03F 3/2175: {using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence)}
- H03F 2200/03: the amplifier being designed for audio applications
- H03F 2200/171: A filter circuit coupled to the output of an amplifier
- G10L: SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
- H03F: AMPLIFIERS

## Abstract

A method may include receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit, detecting an invalid state associated with the stream, and responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.

## Claims

### Claim 1

A method comprising:
receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit;
detecting an invalid state associated with the stream; and
responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
a number of quantization levels represented by an encoded datagram is equal to a power of two of a number of bits in the encoded datagram; and
detecting the invalid state comprises detecting an invalid transition between successive datagrams of one of the first channel and the second channel.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
a number of quantization levels represented by an encoded datagram is less than a power of two of a number of bits in the encoded datagram; and
detecting the invalid state comprises detecting an invalid datagram in one of the first channel and the second channel.

### Claim 4 (depends on 1)

The method of claim 1, further comprising, responsive to detecting the invalid state, modifying the clock to align with the boundaries of each encoded datagram.

### Claim 5 (depends on 4)

The method of claim 4, wherein modifying the clock to align with the boundaries of each encoded datagram comprises modifying the clock such that a PDM output delay for a PDM interface circuit configured to receive the stream is approximately zero.

### Claim 6

A system comprising:
an input configured to receive a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit; and
a processing subsystem configured to:
detect an invalid state associated with the stream; and
responsive to detecting the invalid state, determine boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.

### Claim 7 (depends on 6)

The system of claim 6, wherein:
a number of quantization levels represented by an encoded datagram is equal to a power of two of a number of bits in the encoded datagram; and
detecting the invalid state comprises detecting an invalid transition between successive datagrams of one of the first channel and the second channel.

### Claim 8 (depends on 6)

The system of claim 6, wherein:
a number of quantization levels represented by an encoded datagram is less than a power of two of a number of bits in the encoded datagram; and
detecting the invalid state comprises detecting an invalid datagram in one of the first channel and the second channel.

### Claim 9 (depends on 6)

The system of claim 6, wherein the processing subsystem is further configured to, responsive to detecting the invalid state, modify the clock to align with the boundaries of each encoded datagram.

### Claim 10 (depends on 9)

The system of claim 9, wherein modifying the clock to align with the boundaries of each encoded datagram comprises modifying the clock such that a PDM output delay for a PDM interface circuit configured to receive the stream is approximately zero.