# US 10,770,025 B2 · Method for transmitting and receiving data in display device and display panel drive device

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- Number: US 10,770,025 B2
- Document ID: US10770025B2
- Status: Granted
- Kind: B2
- Application number: 16/205,826
- Filed: 2018-11-30
- Published: 2019-06-06
- Granted: 2020-09-08
- Earliest claimed: 2017-12-04
- Assignees: Silicon Works Co., Ltd.
- Applicants: Silicon Works Co., Ltd.
- Inventors: Myung Yu Kim; Kwan Hee Lee; Young Woong Kim; Hyun Kyu Jeon
- Web page: https://patentgrep.com/patent/US10770025B2

## CPC

- G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)}
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0252: Improving the response speed
- G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD
- G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof
- G09G 2340/02: Handling of images in compressed format, e.g. JPEG, MPEG
- G09G 2370/00: Aspects of data communication
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An embodiment provides a display panel drive device that receives image data in a plurality of image reception periods within one frame period and retrains a data link according to link data received in an interval between the image reception periods.

## Claims

### Claim 1

A data drive device in a display device, the data drive device comprising:
a data reception circuit configured to train a communication clock according to a received clock pattern, to receive first link data in accordance with the communication clock, to train a data link according to the first link data, to receive image data in a plurality of image reception periods within one frame period, to sort the image data in accordance with the data link, to receive second link data in a link reception period disposed between the plurality of image reception periods, and to retrain the data link according to the second link data; and
a data voltage drive circuit configured to generate a data voltage by converting the image data and to supply the data voltage to each sub-pixel.

### Claim 2 (depends on 1)

The data drive device of claim 1, wherein the one frame period comprises a plurality of horizontal (H) time periods respectively corresponding to a plurality of lines on a display panel, and
the plurality of H time periods comprise a setting reception period for receiving setting data, the image reception period, and the link reception period.

### Claim 3 (depends on 2)

The data drive device of claim 2, wherein, when the data link that is determined as an error is restored in the link reception period of a Jth H time period (J is a natural number) among the plurality of H time periods, a process corresponding to the setting reception period or the image reception period of a (J+1)th H time period is normally performed subsequently.

### Claim 4 (depends on 1)

The data drive device of claim 1, wherein the data reception circuit checks the image data or the second link data, and generates a fail signal when the image data or the second link data is against a predefined rule.

### Claim 5 (depends on 4)

The data drive device of claim 4, wherein the data reception circuit counts the fail signal, and changes a state of a lock signal connected to an outside when the fail signal occurs N times or more (N is a natural number).

### Claim 6 (depends on 5)

The data drive device of claim 5, wherein the data reception circuit retrains the communication clock and the data link when changing the state of the lock signal.

### Claim 7 (depends on 1)

The data drive device of claim 1, wherein the data reception circuit trains the communication clock by a phase-locked loop (PLL) method.

### Claim 8 (depends on 1)

The data drive device of claim 1, wherein the data reception circuit sorts the image data per byte, decodes the image data sorted per byte into a DC balance code, descrambles the decoded image data, and sorts the descrambled image data per pixel.

### Claim 9 (depends on 1)

The data drive device of claim 1, wherein the first link data and the second link data comprise a plurality of symbols, and
the data reception circuit sorts the image data per byte using one symbol among the plurality of symbols and sorts the image data per pixel using at least two or more symbols among the plurality of symbols.

### Claim 10 (depends on 1)

The data drive device of claim 1, wherein the data voltage drive circuit supplies the data voltage in the link reception period.

### Claim 11 (depends on 1)

The data drive device of claim 1, wherein the data voltage drive circuit supplies the data voltage according to a periodic signal indicating one point in the link reception period.

### Claim 12 (depends on 1)

The data drive device of claim 1, wherein the data voltage has a greater voltage range than that of the image data or the link data.

### Claim 13 (depends on 1)

The data drive device of claim 1, wherein the data reception circuit checks the image data or the second link data, generates a fail signal when the image data or the second link data is against a predefined rule, changes a state of a lock signal connected to an outside when the fail signal occurs N times or more (N is a natural number), and re-receives the clock pattern after changing the state of the lock signal.

### Claim 14

A data processing device comprising:
a data processor configured to encode image data; and
a data transmitter configured to transmit a clock pattern, to transmit first link data, to transmit the image data in a plurality of image transmission periods within one frame period, to transmit second link data in a link transmission period disposed between the plurality of image transmission periods, and to retransmit the clock pattern and the first link data when a state of a received lock signal is changed.

### Claim 15 (depends on 14)

The data processing device of claim 14, wherein the one frame period comprises a plurality of horizontal (H) time periods respectively corresponding to a plurality of lines on a display panel, and
the plurality of H time periods comprise a setting reception period for receiving setting data, the image reception period, and the link reception period.

### Claim 16

A display drive system comprising:
a data processing device configured to transmit a clock pattern, to transmit first link data, to transmit image data in a plurality of image transmission periods within one frame period, and to transmit second link data in a link transmission period disposed between the image transmission periods; and
a data drive device configured to train a communication clock according to the received clock pattern, to receive the first link data in accordance with the communication clock, to train a data link according to the first link data, to receive the image data in a plurality of image reception periods, to sort the image data in accordance with the data link, to receive the second link data in a link reception period disposed between the plurality of image reception periods, and to retrain the data link according to the second link data.
