# US 10,770,020 B2 · Display panel

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- Number: US 10,770,020 B2
- Document ID: US10770020B2
- Status: Granted
- Kind: B2
- Application number: 16/553,642
- Filed: 2019-08-28
- Published: 2019-12-26
- Granted: 2020-09-08
- Earliest claimed: 2009-11-26
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Jae-Hoon Lee; Seung-Hwan Moon; Yong-Soon Lee; Young-Su Kim; Chang-Ho Lee; Whee-Won Lee; Jun-Yong Song; Yu-Han Bae
- Web page: https://patentgrep.com/patent/US10770020B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

## Claims

### Claim 1

A display device comprising:
a display area including a gate line;
a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
wherein a stage of the plurality of stages comprises:
a clock input terminal to which a clock signal is input;
a first low voltage terminal to which a first low voltage is input;
a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
a first input terminal to which at least one transmission signal from a previous stage is input;
a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
a fifth transistor including a control terminal connected to the first input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected the second node; and
a tenth transistor including a control terminal, an input terminal, and an output terminal, wherein the input terminal of the tenth transistor is connected to the second low voltage terminal, and the output terminal of the tenth transistor is connected to the first node,
wherein a voltage level of the gate-off voltage includes the first low voltage.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the control terminal of the tenth transistor is connected to the second node.

### Claim 3 (depends on 1)

The display device of claim 1, wherein the stage further comprises:
a second input terminal to which at least one transmission signal from one of next stages is input; and
a sixth transistor including a control terminal connected to the second input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node.

### Claim 4 (depends on 3)

The display device of claim 3, wherein the stage further comprises:
a third input terminal to which at least one transmission signal from one of next stages is input; and
a second transistor including a control terminal connected to the third input terminal, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal.

### Claim 5 (depends on 4)

The display device of claim 4, wherein the stage further comprises:
a ninth transistor including a control terminal connected to the third input terminal, and an input terminal connected to the first node; and
a sixteenth transistor including a control terminal and an input terminal that are connected to an output terminal of the ninth transistor, and an output terminal connected to the second low voltage terminal.

### Claim 6 (depends on 1)

The display device of claim 1, wherein the stage further comprises:
a transmission signal output terminal which outputs a transmission signal of the stage; and
an eleventh transistor including a control terminal connected to the second node, an input terminal connected to the transmission signal output terminal, and an output terminal connected to the second low voltage terminal.

### Claim 7 (depends on 1)

The display device of claim 1, wherein a voltage level of the gate-off voltage does not include the second low voltage.

### Claim 8

A display device comprising:
a display area including a gate line;
a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
wherein a stage of the plurality of stages comprises:
a clock input terminal to which a clock signal is input;
a first low voltage terminal to which a first low voltage is input;
a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
a first input terminal to which at least one transmission signal from a previous stage is input;
a second input terminal to which at least one transmission signal from one of next stages is input;
a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
a sixth transistor including a control terminal connected to the second input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node; and
a fifth transistor including a control terminal, an input terminal, and an output terminal, wherein the input terminal of the fifth transistor is connected to the second low voltage terminal, and the output terminal of the fifth transistor is connected to the second node,
wherein a voltage level of the gate-off voltage includes the first low voltage.

### Claim 9 (depends on 8)

The display device of claim 8, wherein the control terminal of the fifth transistor is connected to the first input terminal.

### Claim 10 (depends on 8)

The display device of claim 8, wherein the stage further comprises:
a tenth transistor including a control terminal connected to the second node, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node.

### Claim 11 (depends on 8)

The display device of claim 8, wherein the stage further comprises:
a third input terminal to which at least one transmission signal from one of next stages is input; and
a second transistor including a control terminal connected to the third input terminal, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal.

### Claim 12 (depends on 11)

The display device of claim 11, wherein the stage further comprises:
a ninth transistor including a control terminal connected to the third input terminal, and an input terminal connected to the first node; and
a sixteenth transistor including a control terminal and an input terminal that are connected to an output terminal of the ninth transistor, and an output terminal connected to the second low voltage terminal.

### Claim 13 (depends on 8)

The display device of claim 8, wherein the stage further comprises:
a transmission signal output terminal which outputs a transmission signal of the stage; and
an eleventh transistor including a control terminal connected to the second node, an input terminal connected to the transmission signal output terminal, and an output terminal connected to the second low voltage terminal.

### Claim 14 (depends on 8)

The display device of claim 8, wherein a voltage level of the gate-off voltage does not include the second low voltage.

### Claim 15

A display device comprising:
a display area including a gate line;
a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
wherein a stage of the plurality of stages comprises:
a clock input terminal to which a clock signal is input;
a first low voltage terminal to which a first low voltage is input;
a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
a first input terminal to which at least one transmission signal from a previous stage is input;
a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
a tenth transistor including a control terminal connected to the second node, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node;
a transmission signal output terminal which outputs a transmission signal of the stage; and
an eleventh transistor including a control terminal connected to the second node, an input terminal connected to the transmission signal output terminal, and an output terminal connected to the second low voltage terminal,
wherein a voltage level of the gate-off voltage includes the first low voltage.

### Claim 16 (depends on 15)

The display device of claim 15, wherein the stage further comprises:
a fifth transistor including a control terminal connected to the first input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected the second node.

### Claim 17 (depends on 15)

The display device of claim 15, wherein the stage further comprises:
a second input terminal to which at least one transmission signal from one of next stages is input; and
a sixth transistor including a control terminal connected to the second input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node.

### Claim 18 (depends on 17)

The display device of claim 17, wherein the stage further comprises:
a third input terminal to which at least one transmission signal from one of next stages is input; and
a second transistor including a control terminal connected to the third input terminal, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal.

### Claim 19 (depends on 18)

The display device of claim 18, wherein the stage further comprises:
a ninth transistor including a control terminal connected to the third input terminal, and an input terminal connected to the first node; and
a sixteenth transistor including a control terminal and an input terminal that are connected to an output terminal of the ninth transistor, and an output terminal connected to the second low voltage terminal.

### Claim 20

A display device comprising:
a display area including a gate line;
a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
wherein a stage of the plurality of stages comprises:
a clock input terminal to which a clock signal is input;
a first low voltage terminal to which a first low voltage is input;
a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
a first input terminal to which at least one transmission signal from a previous stage is input;
a second input terminal to which at least one transmission signal from one of next stages is input;
a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal; and
a sixth transistor including a control terminal connected to the second input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node; and
wherein a voltage level of the gate-off voltage includes the first low voltage, and
wherein the voltage level of the second node includes the second low voltage.

### Claim 21 (depends on 20)

The display device of claim 20, wherein the stage further comprises:
a fifth transistor including a control terminal connected to the first input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected the second node.

### Claim 22 (depends on 20)

The display device of claim 20, wherein the stage further comprises:
a tenth transistor including a control terminal connected to the second node, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node.

### Claim 23 (depends on 20)

The display device of claim 20, wherein the stage further comprises:
a third input terminal to which at least one transmission signal from one of next stages is input; and
a second transistor including a control terminal connected to the third input terminal, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal.

### Claim 24 (depends on 23)

The display device of claim 23, wherein the stage further comprises:
a ninth transistor including a control terminal connected to the third input terminal, and an input terminal connected to the first node; and
a sixteenth transistor including a control terminal and an input terminal that are connected to an output terminal of the ninth transistor, and an output terminal connected to the second low voltage terminal.

### Claim 25 (depends on 20)

The display device of claim 20, wherein the stage further comprises:
a transmission signal output terminal which outputs a transmission signal of the stage; and
an eleventh transistor including a control terminal connected to the second node, an input terminal connected to the transmission signal output terminal, and an output terminal connected to the second low voltage terminal.

### Claim 26 (depends on 20)

The display device of claim 20, wherein a voltage level of the gate-off voltage does not include the second low voltage.

### Claim 27

A display device comprising:
a display area including a gate line;
a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
wherein a stage of the plurality of stages comprises:
a clock input terminal to which a clock signal is input;
a first low voltage terminal to which a first low voltage is input;
a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
a first input terminal to which at least one transmission signal from a previous stage is input;
a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal; and
a tenth transistor including a control terminal connected to the second node, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node,
wherein a voltage level of the gate-off voltage includes the first low voltage, and
wherein the voltage level of the second node includes the second low voltage.

### Claim 28 (depends on 27)

The display device of claim 27, wherein the stage further comprises:
a fifth transistor including a control terminal connected to the first input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected the second node.

### Claim 29 (depends on 27)

The display device of claim 27, wherein the stage further comprises:
a second input terminal to which at least one transmission signal from one of next stages is input; and
a sixth transistor including a control terminal connected to the second input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node.

### Claim 30 (depends on 29)

The display device of claim 29, wherein the stage further comprises:
a third input terminal to which at least one transmission signal from one of next stages is input; and
a second transistor including a control terminal connected to the third input terminal, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal.

### Claim 31 (depends on 30)

The display device of claim 30, wherein the stage further comprises:
a ninth transistor including a control terminal connected to the third input terminal, and an input terminal connected to the first node; and
a sixteenth transistor including a control terminal and an input terminal that are connected to an output terminal of the ninth transistor, and an output terminal connected to the second low voltage terminal.

### Claim 32 (depends on 27)

The display device of claim 27, wherein the stage further comprises:
a transmission signal output terminal which outputs a transmission signal of the stage; and
an eleventh transistor including a control terminal connected to the second node, an input terminal connected to the transmission signal output terminal, and an output terminal connected to the second low voltage terminal.