# US 10,770,013 B2 · Semiconductor substrate and driving method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,013 B2 - Document ID: US10770013B2 - Status: Granted - Kind: B2 - Application number: 16/457,934 - Filed: 2019-06-29 - Published: 2020-02-13 - Granted: 2020-09-08 - Earliest claimed: 2018-08-10 - Assignees: Au Optronics Corporation - Applicants: Au Optronics Corporation - Inventors: Che-Chia Chang; Hsien-Chun Wang; Pin-Miao Liu; Ming-Hung Chuang; Ming-Hsien Lee; Shin-Shueh Chen - Web page: https://patentgrep.com/patent/US10770013B2 ## CPC - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G02F 1/136213: {Storage capacitors associated with the pixel electrode} - G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer} - G02F 1/13624: {having more than one switching element per pixel} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G09G 3/3607: {for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels (display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127)} - G09G 3/3659: {the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes} - H10D 30/6723: {having light shields} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/40: characterised by multiple TFTs - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned} - G02F 1/13685: {Top gates} - G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes - G09G 2330/021: Power management, e.g. power saving - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor. ## Claims ### Claim 1 A semiconductor substrate, comprising: a base; a data line, a scan line and a capacitance control line disposed on the base; a first transistor, wherein a first terminal of the first transistor is electrically connected to the data line, and a control terminal of the first transistor is electrically connected to the scan line; a pixel electrode electrically connected to a second terminal of the first transistor; a second transistor, wherein a first terminal of the second transistor is electrically connected to the second terminal of the first transistor; a storage capacitor electrically connected to a second terminal of the second transistor; and a third transistor, wherein a first terminal of the third transistor is electrically connected to the capacitance control line, a control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor. ### Claim 2 (depends on 1) The semiconductor substrate as recited in claim 1, wherein a vertical projection of the second transistor on the base is located between a vertical projection of the first transistor on the base and a vertical projection of the third transistor on the base. ### Claim 3 (depends on 1) The semiconductor substrate as recited in claim 1, wherein a vertical projection of the second transistor on the base is located between a vertical projection of the scan line on the base and a vertical projection of the storage capacitor on the base. ### Claim 4 (depends on 1) The semiconductor substrate as recited in claim 1, wherein the data line extends in a first direction, the scan line extends in a second direction, the control terminal of the second transistor extends in a third direction, and the third direction is intersected with the first direction and the second direction. ### Claim 5 (depends on 4) The semiconductor substrate as recited in claim 4, wherein the second direction and the third direction have an included angle θ, and 0°<θ<60°. ### Claim 6 (depends on 4) The semiconductor substrate as recited in claim 4, wherein the second transistor comprises a semiconductor pattern extending in a fourth direction, and the third direction is intersected with the first direction, the second direction and the fourth direction. ### Claim 7 (depends on 6) The semiconductor substrate as recited in claim 6, wherein the second direction and the fourth direction have an included angle Φ, and 0°<Φ<60°. ### Claim 8 (depends on 6) The semiconductor substrate as recited in claim 6, wherein the third direction and the fourth direction have an included angle α, and 0°<α≤90°. ### Claim 9 (depends on 1) The semiconductor substrate as recited in claim 1, wherein the storage capacitor comprises: an insulating layer disposed on the second terminal of the second transistor, wherein the pixel electrode is disposed on the insulating layer; and a conductive pattern disposed on the insulating layer, separated from the pixel electrode and electrically connected to the second terminal of the second transistor via a contact window of the insulating layer, wherein the conductive pattern overlaps with the second terminal of the second transistor. ### Claim 10 (depends on 1) The semiconductor substrate as recited in claim 1, further comprising: a common electrode disposed on the base, wherein the common electrode overlaps with the pixel electrode to form a display medium capacitor, wherein a capacitance value of the storage capacitor is greater than half of a capacitance value of the display medium capacitor. ### Claim 11 (depends on 1) The semiconductor substrate as recited in claim 1, wherein a semiconductor pattern of the first transistor has a channel width to length ratio W ⁢ ⁢ 1 L ⁢ ⁢ 1 , a semiconductor pattern of the second transistor has a channel width to length ratio W ⁢ ⁢ 2 L ⁢ ⁢ 2 , and ⁢ ⁢ W ⁢ ⁢ 2 L ⁢ ⁢ 2 > W ⁢ ⁢ 1 L ⁢ ⁢ 1 . ### Claim 12 (depends on 11) The semiconductor substrate as recited in claim 11, wherein a semiconductor pattern of the third transistor has a channel width to length ratio W ⁢ ⁢ 3 L ⁢ ⁢ 3 , and ⁢ ⁢ W ⁢ ⁢ 3 L ⁢ ⁢ 3 < ( W ⁢ ⁢ 1 L ⁢ ⁢ 1 ) / ( W ⁢ ⁢ 2 L ⁢ ⁢ 2 ) . ### Claim 13 A driving method, configured to drive a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of pixel structures, each of the pixel structures comprises a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, and a storage capacitor, a first terminal of the first transistor is electrically connected to the data line, a control terminal of the first transistor is electrically connected to the scan line, a second terminal of the first transistor is electrically connected to the pixel electrode, a first terminal of the second transistor is electrically connected to the second terminal of the first transistor, a control terminal of the second transistor is electrically connected to the capacitance control line, a second terminal of the second transistor is electrically connected to the storage capacitor, and the driving method comprises: determining an ON or OFF of at least one second transistor of at least one of the pixel structures according to at least one data signal of at least one data line of the at least one of the pixel structures. ### Claim 14 (depends on 13) The driving method as recited in claim 13, wherein the step of determining the ON or OFF of the at least one second transistor of the at least one of the pixel structures according to the at least one data signal of the at least one data line of the at least one of the pixel structures comprises: enabling the at least one second transistor of the at least one of the pixel structures to be turned ON when determining that a grayscale value of the at least one data signal of the at least one data line of the at least one of the pixel structures is between a first preset value and a second preset value, wherein the first preset value is smaller than the second preset value. ### Claim 15 (depends on 13) The driving method as recited in claim 13, wherein the step of determining the ON or OFF of the at least one second transistor of the at least one of the pixel structures according to the at least one data signal of the at least one data line of the at least one of the pixel structures comprises: enabling the at least one second transistor of the at least one of the pixel structures to be turned OFF when determining that a grayscale value of the at least one data signal of the at least one data line of the at least one of the pixel structures is smaller than a first preset value. ### Claim 16 (depends on 13) The driving method as recited in claim 13, wherein the step of determining the ON or OFF of the at least one second transistor of the at least one of the pixel structures according to the at least one data signal of the at least one data line of the at least one of the pixel structures comprises: enabling the at least one second transistor of the at least one of the pixel structures to be turned OFF when determining that a grayscale value of the at least one data signal of the at least one data line of the at least one of the pixel structures is greater than a second preset value. ### Claim 17 (depends on 13) The driving method as recited in claim 13, wherein the pixel structures are configured to display a plurality of images, and the driving method further comprises: determining the ON or OFF of the second transistors of the pixel structures according to a plurality of characteristics of the images. ### Claim 18 (depends on 17) The driving method as recited in claim 17, wherein the images comprise a first image and a second image, the pixel structures comprise a plurality of first pixel structures for displaying the first image and a plurality of second pixel structures for displaying the second image, and the steps of determining the ON or OFF of the second transistors of the pixel structures according to the characteristics of the images comprise: enabling a plurality of second transistors of the first pixel structures to be turned OFF when determining that the first image comprises a gray screen and a white character interspersed in the gray screen; and enabling a plurality of second transistors of the second pixel structures to be turned ON when determining that the second image comprises a full gray screen. ### Claim 19 (depends on 17) The driving method as recited in claim 17, wherein the step of determining the ON or OFF of the second transistors of the pixel structures according to the characteristics of the images comprises: determining the ON or OFF of the second transistors of the pixel structures according to a plurality of frame rates of the images. ### Claim 20 (depends on 19) The driving method as recited in claim 19, wherein the images comprise a first image and a second image, the pixel structures comprise a plurality of first pixel structures for displaying the first image and a plurality of second pixel structures for displaying the second image, and the steps of determining the ON or OFF of the second transistors of the pixel structures according to the frame rates of the images comprise: enabling a plurality of second transistors of the first pixel structures to be turned ON when determining that a frame rate of the first image is equal to or lower than a first preset frequency; and enabling a plurality of second transistors of the second pixel structures to be turned OFF when determining that a frame rate of the of the second image is equal to or higher than a second preset frequency, wherein the first preset frequency is higher than the second preset frequency. ### Claim 21 (depends on 13) The driving method as recited in claim 13, wherein each of a plurality of data signals of the data lines of the pixel structures ranges between a high data potential Vdh and a low data potential Vdl, each of a plurality of scanning signals of the scan lines of the pixel structures ranges between a high scan potential Vgh and a low scan potential Vgl, each of a plurality of control signals of the capacitance control lines of the pixel structures ranges between a high control potential Vch and a low control potential Vcl, Vdh