# US 10,770,000 B2 · Pixel circuit, driving method, display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,000 B2 - Document ID: US10770000B2 - Status: Granted - Kind: B2 - Application number: 16/096,138 - Filed: 2018-04-24 - Published: 2019-11-21 - Granted: 2020-09-08 - Earliest claimed: 2017-05-31 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Shengji Yang; Xue Dong; Jing Lv; Xiaochuan Chen; Minghua Xuan; Lei Wang; Dongni Liu; Li Xiao; Jie Fu; Pengcheng Lu - Web page: https://patentgrep.com/patent/US10770000B2 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 3/3266: Details of drivers for scan electrodes - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0439: Pixel structures - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel circuit, a driving method, a display panel and a display device. The pixel circuit includes: at least two pixel sub-circuits, a data line, a first scan line, a second scan line, a third scan line and a light-emitting control line. The pixel sub-circuit includes: a light-emitting control sub-circuit, a node reset sub-circuit, a drive control sub-circuit, a write sub-circuit and a light emitting device. The light-emitting control sub-circuit is configured to provide a signal provided by the first voltage signal end to a first node; the node reset sub-circuit is configured to form a conductive path between the first node and a second node; the write sub-circuit is configured to write a data signal provided by the data signal end and a threshold voltage to the second node; and the drive control sub-circuit is configured to drive the light emitting device to emit light. ## Claims ### Claim 1 A display panel, comprising a plurality of pixel circuits, wherein each of the plurality of pixel circuits comprises at least two pixel sub-circuits; and a data line, a first scan line, a second scan line, a third scan line and a light-emitting control line corresponding to the pixel circuit, each of the pixel sub-circuits comprises: a light-emitting control sub-circuit, a node reset sub-circuit, a drive control sub-circuit, a write sub-circuit and a light emitting device, and in each of the pixel sub-circuits: the light-emitting control sub-circuit is connected with a first voltage signal end, a light-emitting control end and a first node respectively: the light-emitting control sub-circuit is configured to provide a signal provided by the first voltage signal end to the first node under a control of the light-emitting control end; the node reset sub-circuit is connected with a first scanning signal end, the first node and a second node respectively: the node reset sub-circuit is configured to form a conductive path between the first node and the second node under a control of the first scanning signal end; the write sub-circuit is connected with a second scanning signal end, a data signal end and the second node respectively: the write sub-circuit is configured to write a data signal provided by the data signal end and a threshold voltage to the second node under a control of the second scanning signal end; the drive control sub-circuit is connected with the first node, the second node and the light emitting device respectively; the drive control sub-circuit is configured to drive the light emitting device to emit light under a control of the second node; and the light emitting device is connected between the drive control sub-circuit and the second voltage signal end, the plurality of the pixel circuits is arranged in a matrix; each column of the pixel circuits shares a single data line, and each row of the pixel circuits shares a single first scan line, a single second scan line, a single third scam line and a single light-emitting control line, the plurality of pixel circuits comprises N rows of pixel circuits, N is an integer greater than 3, and the first scan line of an (n+1)th row of the pixel circuits is reused as the second scan line of an nth row of the pixel circuits, the first scan line of an (n+2)th row of the pixel circuits is reused as the third scan line of an nth row of the pixel circuits, n is an integer greater than or equal to 1, and n is less than or equal to N−2. ### Claim 2 (depends on 1) A display device comprising the display panel according to claim 1. ### Claim 3 (depends on 1) The display panel according to claim 1, wherein each of the pixel sub-circuits further comprises a regulating sub-circuit, and in each of the pixel sub-circuits, the regulating sub-circuit is connected between the second node and the second voltage signal end, and is configured to maintain a potential of the second node. ### Claim 4 (depends on 3) The display panel according to claim 3, wherein the regulating sub-circuit of each of the pixel sub-circuits comprises a first capacitor, and the first capacitor is connected between the second node and the second voltage signal end. ### Claim 5 (depends on 3) The display panel according to claim 3, wherein the data signal end of each of the pixel sub-circuits is connected with the data line, the first scanning signal end of each of the pixel sub-circuits is connected with the first scanning signal line, the light-emitting control end of each of the pixel sub-circuits is connected with the light-emitting control line, the second scanning signal end of a first pixel sub-circuit of the at least two pixel sub-circuits is connected with the second scanning signal line, and the second scanning signal end of a second pixel sub-circuit of the at least two pixel sub-circuits is connected with the third scanning signal line. ### Claim 6 (depends on 3) The display panel according to claim 3, wherein the light-emitting control sub-circuit of each of the pixel sub-circuits comprises a first switching transistor, and a gate of the first switching transistor is connected with the light-emitting control end, a source of the first switching transistor is connected with the first voltage signal end, and a drain of the first switching transistor is connected with the first node. ### Claim 7 (depends on 3) The display panel according to claim 3, wherein the node reset sub-circuit of each of the pixel sub-circuits comprises a second switching transistor, and a gate of the second switching transistor is connected with the first scanning signal end, a source of the second switching transistor is connected with the first node, and a drain of the second switching transistor is connected with the second node. ### Claim 8 (depends on 3) The display panel according to claim 3, wherein the write sub-circuit of each of the pixel sub-circuits comprises: a third switching transistor and a fourth switching transistor, and a gate of the third switching transistor is connected with the second scanning signal end, a source of the third switching transistor is connected with the data signal end, and a drain of the third switching transistor is connected with a source of the fourth switching transistor, and a gate of the fourth switching transistor is connected with the second node, a source of the fourth switching transistor is connected with the drain of the third switching transistor, and a drain of the fourth switching transistor is connected with the second node. ### Claim 9 (depends on 1) The display panel according to claim 1, wherein the data signal end of each of the pixel sub-circuits is connected with the data line, the first scanning signal end of each of the pixel sub-circuits is connected with the first scanning signal line, the light-emitting control end of each of the pixel sub-circuits is connected with the light-emitting control line, the second scanning signal end of a first pixel sub-circuit of the at least two pixel sub-circuits is connected with the second scanning signal line, and the second scanning signal end of a second pixel sub-circuit of the at least two pixel sub-circuits is connected with the third scanning signal line. ### Claim 10 (depends on 9) The display panel according to claim 9, wherein the light-emitting control sub-circuit of each of the pixel sub-circuits comprises a first switching transistor, and a gate of the first switching transistor is connected with the light-emitting control end, a source of the first switching transistor is connected with the first voltage signal end, and a drain of the first switching transistor is connected with the first node. ### Claim 11 (depends on 9) The display panel according to claim 9, wherein the node reset sub-circuit of each of the pixel sub-circuits comprises a second switching transistor, and a gate of the second switching transistor is connected with the first scanning signal end, a source of the second switching transistor is connected with the first node, and a drain of the second switching transistor is connected with the second node. ### Claim 12 (depends on 9) The display panel according to claim 9, wherein the write sub-circuit of each of the pixel sub-circuits comprises: a third switching transistor and a fourth switching transistor, and a gate of the third switching transistor is connected with the second scanning signal end, a source of the third switching transistor is connected with the data signal end, and a drain of the third switching transistor is connected with a source of the fourth switching transistor, and a gate of the fourth switching transistor is connected with the second node, a source of the fourth switching transistor is connected with the drain of the third switching transistor, and a drain of the fourth switching transistor is connected with the second node. ### Claim 13 (depends on 1) The display panel according to claim 1, wherein the light-emitting control sub-circuit of each of the pixel sub-circuits comprises a first switching transistor, and a gate of the first switching transistor is connected with the light-emitting control end, a source of the first switching transistor is connected with the first voltage signal end, and a drain of the first switching transistor is connected with the first node. ### Claim 14 (depends on 13) The display panel according to claim 13, wherein all of the switching transistors are N-type transistors. ### Claim 15 (depends on 13) The display panel according to claim 13, wherein the node reset sub-circuit of each of the pixel sub-circuits comprises a second switching transistor, and a gate of the second switching transistor is connected with the first scanning signal end, a source of the second switching transistor is connected with the first node, and a drain of the second switching transistor is connected with the second node. ### Claim 16 (depends on 1) The display panel according to claim 1, wherein the node reset sub-circuit of each of the pixel sub-circuits comprises a second switching transistor, and a gate of the second switching transistor is connected with the first scanning signal end, a source of the second switching transistor is connected with the first node, and a drain of the second switching transistor is connected with the second node. ### Claim 17 (depends on 1) The display panel according to claim 1, wherein the write sub-circuit of each of the pixel sub-circuits comprises: a third switching transistor and a fourth switching transistor, and a gate of the third switching transistor is connected with the second scanning signal end, a source of the third switching transistor is connected with the data signal end, and a drain of the third switching transistor is connected with a source of the fourth switching transistor, and a gate of the fourth switching transistor is connected with the second node, a source of the fourth switching transistor is connected with the drain of the third switching transistor, and a drain of the fourth switching transistor is connected with the second node. ### Claim 18 (depends on 1) The display panel according to claim 1, wherein the drive control sub-circuit of each of the pixel sub-circuits comprises a drive transistor, and a gate of the drive transistor is connected with the second node, a source of the drive transistor is connected with the first node, and a drain of the drive transistor is connected with the light emitting device.