# US 10,769,987 B2 · Display device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,769,987 B2
- Document ID: US10769987B2
- Status: Granted
- Kind: B2
- Application number: 15/439,133
- Filed: 2017-02-22
- Published: 2017-12-07
- Granted: 2020-09-08
- Earliest claimed: 2016-06-01
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Seung Kyu Lee; Tae Hoon Kwon; Min Ku Lee; Ji Hyun Ka; Jin Tae Jeong; Seung Ji Cha
- Web page: https://patentgrep.com/patent/US10769987B2

## CPC

- G09G 3/3225: using an active matrix
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 2300/0439: Pixel structures
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display device includes first pixels in a first pixel region and connected to first scan lines and second pixels in a second pixel region connected to second scan lines. The second pixel has a width less than the first pixel region. The display device also includes a first scan driver to supply first scan signals to the first scan lines, a second scan driver to supply second scan signals to the second scan lines, a first signal line to supply a first driving signal to the first scan driver and the second scan driver, and a signal delay circuit connected to the first signal line to delay the first driving signal.

## Claims

### Claim 1

A display device, comprising:
first pixels in a first pixel region and connected to first scan lines;
second pixels in a second pixel region having a width less than the first pixel region, the second pixels connected to second scan lines;
a first scan driver to supply first scan signals to the first scan lines in a first scan period;
a second scan driver to supply second scan signals to the second scan lines in a second scan period;
a first signal line, connected to the first scan driver and the second scan driver, to supply a first driving signal to the first scan driver and the second scan driver;
a data driver to supply data signals to the first pixels and the second pixels through data lines; and
a signal delay circuit to delay the first driving signal in the second scan period and not to delay the first driving signal in the first scan period.

### Claim 2 (depends on 1)

The display device as claimed in claim 1, wherein a number of second pixels in horizontal lines of the second pixel region is less than a number of first pixels in horizontal lines of the first pixel region.

### Claim 3 (depends on 1)

The display device as claimed in claim 1, wherein a length of the second scan lines is less than a length of the first scan lines.

### Claim 4 (depends on 1)

The display device as claimed in claim 1, wherein the first driving signal includes at least one clock signal.

### Claim 5 (depends on 4)

The display device as claimed in claim 4, wherein:
the first signal line includes a first clock signal line and a second clock signal line, and
the first clock signal line and the second clock signal line are connected to the signal delay circuit.

### Claim 6 (depends on 1)

The display device as claimed in claim 1, wherein the signal delay circuit includes:
a signal delay circuit element; and
a signal delay control transistor to control electrical connection between the signal delay circuit element and the first signal line.

### Claim 7 (depends on 6)

The display device as claimed in claim 6, wherein the signal delay circuit element includes at least one of a resistor or a capacitor.

### Claim 8 (depends on 7)

The display device as claimed in claim 7, wherein the signal delay control transistor turns on and off based on a control signal from a timing controller.

### Claim 9 (depends on 7)

The display device as claimed in claim 7, wherein the signal delay control transistor maintains an on state in a first period in which the second scan signals are supplied and maintains an off state in a second period in which the first scan signals are supplied.

### Claim 10 (depends on 9)

The display device as claimed in claim 9, wherein:
the first scan driver supplies the first scan signals to the first scan lines based on the first driving signal in the second period, and
the second scan driver supplies the second scan signals to the second scan lines based on the first driving signal delayed in the first period.

### Claim 11 (depends on 6)

The display device as claimed in claim 6, further comprising:
third pixels in a third pixel region and connected to third scan lines; and
a third scan driver, connected to the first signal line, to receive the first driving signal and to supply third scan signals to the third scan lines.

### Claim 12 (depends on 11)

The display device as claimed in claim 11, wherein:
the third pixel region has a width less than the first pixel region, and
the second pixel region and the third pixel region are at one side of the first pixel region and separate from each other.

### Claim 13 (depends on 12)

The display device as claimed in claim 12, wherein the signal delay control transistor maintains an on state in a first period in which the second scan signals and the third scan signals are supplied and maintains an off state in a second period in which the first scan signals are supplied.

### Claim 14

A display device, comprising:
first pixels in a first pixel region and connected to first scan lines;
second pixels in a second pixel region having a width less than the first pixel region, the second pixels are connected to second scan lines;
third pixels in a third pixel region having a width less than the second pixel region, the third pixels connected to third scan lines;
a first scan driver to supply first scan signals to the first scan lines in a first scan period;
a second scan driver to supply second scan signals to the second scan lines in a second scan period;
a third scan driver to supply third scan signals to the third scan lines;
a first signal line, connected to the first scan driver, the second scan driver, and the third scan driver, to supply a first driving signal to the first scan driver, the second scan driver, and the third scan driver;
a data driver to supply data signals to the first pixels and the second pixels through data lines; and
a first signal delay circuit and a second signal delay circuit to delay the first driving signal in the second scan period and not to delay the first driving signal in the first scan period.

### Claim 15 (depends on 14)

The display device as claimed in claim 14, wherein the first signal delay circuit and the second signal delay circuit operate in a first period in which the third scan signals are supplied.

### Claim 16 (depends on 14)

The display device as claimed in claim 14, wherein the first signal delay circuit operates and the second signal delay circuit stops operating in a second period in which the second scan signals are supplied.

### Claim 17 (depends on 14)

The display device as claimed in claim 14, wherein:
a number of third pixels in horizontal lines of the third pixel region is less than a number of second pixels in horizontal lines of the second pixel region, and
a number of second pixels in horizontal lines of the second pixel region is less than a number of first pixels provided in horizontal lines of the first pixel region.

### Claim 18 (depends on 14)

The display device as claimed in claim 14, wherein:
a length of the third scan lines is less than a length of the second scan lines, and a length of the second scan lines is less than a length of the first scan lines.

### Claim 19 (depends on 14)

The display device as claimed in claim 14, wherein:
the first signal delay circuit includes a first signal delay circuit element and a first signal delay control transistor to control electrical connection between the first signal delay circuit element and the first signal line, and
the second signal delay circuit includes a second signal delay circuit element and a second signal delay control transistor to control electrical connection between the second signal delay circuit element and the first signal line.

### Claim 20 (depends on 19)

The display device as claimed in claim 19, wherein each of the first signal delay circuit element and the second signal delay circuit element includes at least one of a resistor or a capacitor.

### Claim 21 (depends on 19)

The display device as claimed in claim 19, wherein the first signal delay control transistor and the second signal delay control transistor maintain on states in a first period in which the third scan signals are supplied.

### Claim 22 (depends on 21)

The display device as claimed in claim 21, wherein the first signal delay control transistor maintains an on state and the second signal delay control transistor maintains an off state in a second period in which the second scan signals are supplied.

### Claim 23 (depends on 22)

The display device as claimed in claim 22, wherein the first signal delay control transistor and the second signal delay control transistor maintain off states in a third period in which the first scan signals are supplied.

### Claim 24 (depends on 23)

The display device as claimed in claim 23, wherein the first period, the second period, and the third period are sequential periods.

### Claim 25 (depends on 1)

The display device as claimed in claim 1, wherein:
the signal delay circuit is electrically connected to the first signal line to delay the first driving signal while the second scan signals are supplied to the second scan lines, and
the signal delay circuit is electrically separated from the first signal line so as not to delay the first driving signal while the first scan signals are supplied to the first scan lines.