# US 10,769,977 B2 · Shift register and driving method of the same, emission driving circuit, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,977 B2 - Document ID: US10769977B2 - Status: Granted - Kind: B2 - Application number: 16/100,474 - Filed: 2018-08-10 - Published: 2019-10-24 - Granted: 2020-09-08 - Earliest claimed: 2018-04-20 - Assignees: Shanghai Tianma Am-Oled Co., Ltd. - Applicants: Shanghai Tianma AM-OLED Co., Ltd. - Inventors: Dongxu Xiang; Yue Li; Renyuan Zhu; Yana Gao; Xing Yao Zhou; Juan Zhu; Zhonglan Cai; Yilin Xu; Gaojun Huang - Web page: https://patentgrep.com/patent/US10769977B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 3/3674: {Details of drivers for scan electrodes} - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure provides a shift register. The shift register includes: a first node control module configured to control level at a first node based on a first clock signal and a second clock signal; a second node control module configured to control level at a second node based on level at the first node, the first clock signal, the second clock signal, a first low level signal and a high level signal; an output control module configured to control an output terminal to output high or low level based on level at the first node, level at the second node, the high level signal and a second low level signal; and a carry control module configured to control a carry terminal to output high or low level based on level at the second node, level at the output terminal, the high level signal and the second low level signal. ## Claims ### Claim 1 An emission driving circuit, comprising a shift register, wherein the shift register comprises: a first node control module electrically connected to an input signal terminal, a first clock signal terminal, a second clock signal terminal and a high level signal terminal, and configured to provide an input signal or a high level signal to a first node based on a first clock signal and a second clock signal, so as to control a level at the first node; a second node control module electrically connected to the first node, the first clock signal terminal, the second clock signal terminal, a first low level signal terminal and the high level signal terminal, and configured to control a level at a second node based on the level at the first node, the first clock signal, the second clock signal, a first low level signal and the high level signal; an output control module electrically connected to the first node, the second node, the high level signal terminal and a second low level signal terminal, and configured to control an output terminal to output a high level or a low level based on the level at the first node, the level at the second node, the high level signal and a second low level signal; and a carry control module electrically connected to the second node, the high level signal terminal, the output terminal and the second low level signal terminal, and configured to control a carry terminal to output a high level or a low level based on the level at the second node, a level at the output terminal, the high level signal and the second low level signal, wherein the output control module comprises a ninth transistor, a tenth transistor; the carry control module comprises an eleventh transistor and a twelfth transistor, wherein the ninth transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the output terminal, the tenth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the second low level signal terminal and a second terminal electrically connected to the output terminal, wherein the eleventh transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the carry terminal, and the twelfth transistor has a control terminal electrically connected to the output terminal, a first terminal electrically connected to the second low level signal terminal and a second terminal electrically connected to the carry terminal, wherein in a first phase when the input signal provided by the input signal terminal is at a high level, the first clock signal provided by the first clock signal terminal is at a low level, and the second clock signal provided by the second clock signal terminal is at a high level, the first node control module provides a high level at the first node, the second node control module maintains the second node at a high level in a previous phase, the output control module maintains the output terminal at a low level outputted in a previous phase based on the high level at the first node and the high level at the second node, and the carry control module controls the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, in a second phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a high level, and the second clock signal provided by the second clock signal terminal is at a low level, the first node control module provides a high level at the first node, the second node control module provides a low level at the second node, the output control module controls the output terminal to output a high level based on the high level at the first node and the low level at the second node, and the carry control module controls the carry terminal to output a high level based on the low level at the second node and the high level at the output terminal, in a third phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a low level, the second clock signal provided by the second clock signal terminal is at a high level, the first node control module provides a low level at the first node, the second node control module provides a high level at the second node, the output control module controls the output terminal to output a low level based on the low level at the first node and the high level at the second node, and the carry control module controls the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, and in a fourth phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a high level, the second clock signal provided by the second clock signal terminal is at a low level, the first node control module provides a low level at the first node, the second node control module provides a high level at the second node, the output control module controls the output terminal to output a low level based on the low level at the first node and the high level at the second node, and the carry control module controls the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal. ### Claim 2 (depends on 1) The emission driving circuit according to claim 1, wherein a low level of the first low level signal is smaller than a low level of the second low level signal. ### Claim 3 (depends on 1) The emission driving circuit according to claim 1, wherein a low level of the first low level signal is equal to a low level of the second low level signal. ### Claim 4 (depends on 1) The emission driving circuit according to claim 1, wherein the first node control module comprises a first transistor, a second transistor and a third transistor, and wherein the first transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the input signal terminal, and a second terminal electrically connected to the first node, the second transistor has a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to a second terminal of the third transistor, and a second terminal electrically connected to the first node, and the third transistor has a control terminal electrically connected to a third node, and a first terminal electrically connected to the high level signal terminal. ### Claim 5 (depends on 4) The emission driving circuit according to claim 4, wherein the first node control module further comprises a first capacitor having a first terminal electrically connected to the second clock signal terminal and a second terminal electrically connected to the first node. ### Claim 6 (depends on 1) The emission driving circuit according to claim 1, wherein the second node control module comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor and a third capacitor, and wherein the fourth transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the first low level signal terminal, and a second terminal electrically connected to a third node, the fifth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the first clock signal terminal, and a second terminal electrically connected to the third node, the sixth transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the second clock signal terminal, and a second terminal electrically connected to a fourth node, the seventh transistor has a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the fourth node, and a second terminal electrically connected to the second node, the eighth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the second node, the second capacitor has a first terminal electrically connected to the high level signal terminal and a second terminal electrically connected to the second node, and the third capacitor has a first terminal electrically connected to the third node and a second terminal electrically connected to the fourth node. ### Claim 7 (depends on 1) The emission driving circuit according to claim 1, wherein the eleventh transistor has a channel with a width to length ratio within a range of 1˜5, and the twelfth transistor has a channel with a width to length ratio within a range of 1˜5. ### Claim 8 A driving method of an emission driving circuit, applicable in an emission driving circuit comprising: a first node control module electrically connected to an input signal terminal, a first clock signal terminal, a second clock signal terminal and a high level signal terminal, and configured to provide an input signal or a high level signal to a first node based on a first clock signal and a second clock signal, so as to control a level at the first node; a second node control module electrically connected to the first node, the first clock signal terminal, the second clock signal terminal, a first low level signal terminal and the high level signal terminal, and configured to control a level at a second node based on the level at the first node, the first clock signal, the second clock signal, a first low level signal and the high level signal; an output control module electrically connected to the first node, the second node, the high level signal terminal and a second low level signal terminal, and configured to control an output terminal to output a high level or a low level based on the level at the first node, the level at the second node, the high level signal and a second low level signal; and a carry control module electrically connected to the second node, the high level signal terminal, the output terminal and the second low level signal terminal, and configured to control a carry terminal to output a high level or a low level based on the level at the second node, a level at the output terminal, the high level signal and the second low level signal, wherein the output control module comprises a ninth transistor, a tenth transistor; the carry control module comprises an eleventh transistor and a twelfth transistor, wherein the ninth transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the output terminal, the tenth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the second low level signal terminal and a second terminal electrically connected to the output terminal, wherein the eleventh transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the carry terminal, and the twelfth transistor has a control terminal electrically connected to the output terminal, a first terminal electrically connected to the second low level signal terminal and a second terminal electrically connected to the carry terminal, wherein the driving method comprises: providing, by the first node control module, a high level at the first node; maintaining, by the second node control module, the second node at a high level in a previous phase; maintaining, by the output control module, the output terminal at a low level outputted in a previous phase based on the high level at the first node and the high level at the second node; and controlling, by the carry control module, the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, in a first phase when the input signal provided by the input signal terminal is at a high level, the first clock signal provided by the first clock signal terminal is at a low level, and the second clock signal provided by the second clock signal terminal is at a high level, providing, by the first node control module, a high level at the first node; providing, by the second node control module, a low level at the second node; controlling, by the output control module, the output terminal to output a high level based on the high level at the first node and the low level at the second node; and controlling, by the carry control module, the carry terminal to output a high level based on the low level at the second node and the high level at the output terminal, in a second phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a high level, and the second clock signal provided by the second clock signal terminal is at a low level, providing, by the first node control module, a low level at the first node; providing, by the second node control module, a high level at the second node; controlling, by the output control module, the output terminal to output a low level based on the low level at the first node and the high level at the second node; and controlling, by the carry control module, the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, in a third phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a low level, the second clock signal provided by the second clock signal terminal is at a high level, and providing, by the first node control module, a low level at the first node; providing, by the second node control module, a high level at the second node; controlling, by the output control module, the output terminal to output a low level based on the low level at the first node and the high level at the second node; and controlling, by the carry control module, the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, in a fourth phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a high level, the second clock signal provided by the second clock signal terminal is at a low level. ### Claim 9 (depends on 8) The driving method of an emission driving circuit according to claim 8, wherein the eleventh transistor has a channel with a width to length ratio within a range of 1˜5, and the twelfth transistor has a channel with a width to length ratio within a range of 1˜5. ### Claim 10 (depends on 8) The driving method of an emission driving circuit according to claim 8, wherein a low level of the first low level signal is smaller than a low level of the second low level signal. ### Claim 11 (depends on 8) The driving method of an emission driving circuit according to claim 8, wherein a low level of the first low level signal is equal to a low level of the second low level signal.