# US 10,769,837 B2 · Apparatus and method for performing tile-based rendering using prefetched graphics data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,837 B2 - Document ID: US10769837B2 - Status: Granted - Kind: B2 - Application number: 16/111,608 - Filed: 2018-08-24 - Published: 2019-06-27 - Granted: 2020-09-08 - Earliest claimed: 2017-12-26 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yeon-Gon Cho; Woong Seo - Web page: https://patentgrep.com/patent/US10769837B2 ## CPC - G06T 15/005: {General purpose rendering architectures} - G06T 15/04: Texture mapping - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract A graphics processing unit (GPU), configured to perform tile-based rendering using prefetched graphics data, includes a tiler configured to perform binning on a current frame and obtain a first binning bitstream of a first tile among a plurality of tiles of the current frame, a binning correlator configured to determine whether the first tile and a second tile of a previous frame are similar to each other by using the first binning bitstream and a second binning bitstream of the second tile, where the second tile has a same tile ID as the first tile, a prefetcher configured to prefetch second graphics data used to render the second tile by using the tile ID, when it is determined that the first tile and the second tile are similar to each other, and at least one processor configured to render the current frame using the prefetched second graphics data. ## Claims ### Claim 1 A graphics processing unit (GPU) configured to perform tile-based rendering using prefetched graphics data, the GPU comprising: a tiler circuit configured to perform binning on a current frame and obtain a first binning bitstream of a first tile among a plurality of tiles of the current frame; a binning correlator circuit configured to determine whether the first tile and a second tile of a previous frame are similar to each other by comparing bits of the first binning bitstream and a second binning bitstream of the second tile, wherein the second tile has a same tile ID as the first tile; a prefetcher circuit configured to prefetch second graphics data used to render the second tile by using the tile ID, when it is determined that the first tile and the second tile are similar to each other; and at least one processor configured to render the current frame using the prefetched second graphics data, wherein the binning correlator circuit is further configured to determine that the first tile and the second tile are similar to each other when a difference between a sum of bits comprised in the first binning bitstream and a sum of bits comprised in the second binning bitstream is less than or equal to a threshold value. ### Claim 2 (depends on 1) The GPU of claim 1, wherein the threshold value is determined to be a fixed value based on a result of simulating an application. ### Claim 3 (depends on 1) The GPU of claim 1, wherein the threshold value is dynamically adjusted using a cache hit rate received from at least one of an L1 cache and an L2 cache included in the GPU. ### Claim 4 (depends on 1) The GPU of claim 1, wherein each of the first binning bitstream and the second binning bitstream comprises information about a plurality of primitives included in each of the first tile and the second tile. ### Claim 5 (depends on 1) The GPU of claim 1, wherein the prefetcher circuit is further configured to prefetch the second graphics data using second address information and second size information of the second graphics data, and the second address information and the second size information are matched with the tile ID. ### Claim 6 (depends on 5) The GPU of claim 5, wherein the second address information comprises information about at least one of a start address and a last address of a read address that is requested to a memory so as to read the second graphics data in the previous frame, and the second size information is determined based on a difference between the start address and the last address. ### Claim 7 (depends on 1) The GPU of claim 1, wherein the prefetcher circuit is further configured to match, with the tile ID, first address information and first size information of first graphics data used to render the first tile in the current frame, and to store the first address information and the first size information. ### Claim 8 (depends on 7) The GPU of claim 7, wherein each of the first graphics data and the second graphics data comprises at least one of vertex attribute data, texture data, or graphics state data. ### Claim 9 A method of performing tile-based rendering using prefetched graphics data in a graphics processing unit (GPU), the method comprising: performing binning on a current frame and obtaining a first binning bitstream of a first tile among a plurality of tiles of the current frame; determining whether the first tile and a second tile of a previous frame are similar to each other by using the first binning bitstream and a second binning bitstream of the second tile, wherein the second tile has a same tile ID as the first tile; prefetching second graphics data used to render the second tile by using the tile ID when it is determined that the first tile and the second tile are similar to each other; and rendering the current frame using the prefetched second graphics data, wherein the determining comprises determining that the first tile and the second tile are similar to each other when a difference between a sum of bits comprised in the first binning bitstream and a sum of bits comprised in the second binning bitstream is less than or equal to a threshold value. ### Claim 10 (depends on 9) The method of claim 9, wherein the threshold value is determined to be a fixed value based on a result of simulating an application. ### Claim 11 (depends on 9) The method of claim 9, wherein the threshold value is dynamically adjusted using a cache hit rate received from at least one of an L1 cache and an L2 cache included in the GPU. ### Claim 12 (depends on 9) The method of claim 9, wherein each of the first binning bitstream and the second binning bitstream comprises information about a plurality of primitives included in each of the first tile and the second tile. ### Claim 13 (depends on 9) The method of claim 9, wherein the prefetching comprises prefetching the second graphics data using second address information and second size information of the second graphics data, and the second address information and the second size information are matched with the tile ID. ### Claim 14 (depends on 13) The method of claim 13, wherein the second address information comprises information about at least one of a start address and a last address of a read address that is requested to a memory so as to read the second graphics data in the previous frame, and the second size information is determined based on a difference between the last address and the start address. ### Claim 15 (depends on 9) The method of claim 9, further comprising: matching, with the tile ID, first address information and first size information of first graphics data used to render the first tile in the current frame; and storing the first address information and the first size information. ### Claim 16 (depends on 15) The method of claim 15, wherein each of the first graphics data and the second graphics data comprises at least one of vertex attribute data, texture data, or graphics state data. ### Claim 17 (depends on 9) The method of claim 9, wherein the prefetching comprises sequentially retrieving an L1 cache, an L2 cache, and dynamic random access memory (DRAM) to prefetch the second graphics data. ### Claim 18 A system on chip (SoC) comprising: a central processing unit (CPU) configured to execute an application by controlling an operation of the SoC; and a graphics processing unit (GPU) configured to perform tile-based rendering using prefetched graphics data, wherein the GPU comprises: a tiler circuit configured to perform binning on a current frame and obtain a first binning bitstream of a first tile among a plurality of tiles of the current frame; a binning correlator circuit configured to determine whether the first tile and a second tile of a previous frame are similar to each other by using the first binning bitstream, a second binning bitstream of the second tile, and a threshold value, wherein the second tile has a same tile ID as the first tile; a prefetcher circuit configured to prefetch second graphics data used to render the second tile by using the tile ID, when it is determined that the first tile and the second tile are similar to each other; and at least one processor configured to render the current frame by using the prefetched second graphics data, wherein the threshold value is dynamically adjusted using a cache hit rate received from at least one of an L1 cache and an L2 cache included in the GPU.