# US 10,769,751 B2 · Single input multiple data processing mechanism

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- Number: US 10,769,751 B2
- Document ID: US10769751B2
- Status: Granted
- Kind: B2
- Application number: 16/543,849
- Filed: 2019-08-19
- Published: 2020-02-06
- Granted: 2020-09-08
- Earliest claimed: 2016-12-21
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Subramaniam Maiyuran; Jorge F. Garcia Pabon; Vikranth Vemulapalli; Chandra S. Gurram; Aditya Navale; Saurabh Sharma
- Web page: https://patentgrep.com/patent/US10769751B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/30181: {Instruction operation extension or modification}
- G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead
- G06F 9/3832: {Value prediction for operands; operand history buffers}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a register file having a plurality of channels to store data and an execution unit to examine data at each of the plurality of channels, read a data value from a first of the plurality of channels upon a determination that each of the plurality of channels has the same data and execute a single input multi data (SIMD) instruction based on the data value.

## Claims

### Claim 1

A processing apparatus, comprising:
a graphics processing unit (GPU), including:
a register file having a plurality of channels to store data, the plurality of channels including a first channel to store first data for an instruction to be executed by a processing resource and a second channel to store second data for the instruction to be executed by the processing resource; and
a processing resource to:
examine the first data and the second data and upon a determination that the first data and the second data are the same, to:
read the first data from the first channel of the plurality of channels; and
generate a scoreboard value to be stored in a scoreboard communicatively coupled to the processing resource, wherein the first scoreboard value indicates that the first data and the second data are the same; and
in response to a determination that the instruction to be executed by the processing resource comprises at least a first source and a second source, to:
perform a logical operation on a first scoreboard value associated with the first source and a second scoreboard value associated with the second source to produce a destination scoreboard value;
write the first data value to the second channel in response to a determination that the destination scoreboard value indicates that first scoreboard value and the second scoreboard value are equal;
generate a flag signal upon a determination that each of the plurality of channels has the same data;
store the flag signal as a scoreboard value, wherein the scoreboard value is accessed upon received a SIMD instruction to be processed by the processing resource;
in response to a determination that the instruction is a one source instruction, retrieve the scoreboard value from the scoreboard as a source scoreboard value and copy the scoreboard value to a destination address in the scoreboard as a destination scoreboard value; and
write a data value resulting from the execution of the instruction to the second channel,
wherein two or more scoreboard values are retrieved from the scoreboard as source scoreboard values upon a determination that the instruction is not a one source instruction, a logical operation is performed on the two or more scoreboard values and a result of the logic is stored in a destination address in the scoreboard as a destination scoreboard value, and the data value in the first channel of the register file is written to the second channel upon a determination that the destination scoreboard value indicates that the two or more scoreboard values have the same value.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the data is written into the second channel upon a determination that the flag signal is stored in the scoreboard.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the data value in the first channel of the register file is written to the second channel upon a determination that the instruction is a one source instruction.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the execution unit executes all channels upon a determination that the destination scoreboard value indicates that the two or more scoreboard values have different values.

### Claim 5

A method comprising:
storing, in a register file having a plurality of channels, first data for an instruction to be executed by an processing resource in a first channel and second data for the instruction to be executed by the processing resource in a second channel; and
in an processing resource communicatively coupled to the register file:
examining the first data and the second data and upon a determination that the first data and the second data are the same:
reading the first data from the first channel of the plurality of channels; and
generating a scoreboard value to be stored in a scoreboard communicatively coupled to the processing resource, wherein the scoreboard value indicates that the first data and the second data are the same; and
in response to a determination that the instruction to be executed by the EU comprises at least a first source and a second source, to:
performing a logical operation on a first scoreboard value associated with the first source and a second scoreboard value associated with the second source to produce a destination scoreboard value; and
writing the first data value to the second channel in response to a determination that the destination scoreboard value indicates that first scoreboard value and the second scoreboard value are equal
generating a flag signal upon a determination that each of the plurality of channels has the same data;
storing the flag signal as a scoreboard value, wherein the scoreboard value is accessed upon received a SIMD instruction to be processed by the processing resource;
in response to a determination that the instruction is a one source instruction, retrieving the scoreboard value from the scoreboard as a source scoreboard value and copying the scoreboard value to a destination address in the scoreboard as a destination scoreboard value; and
writing a data value resulting from the execution of the instruction to the second channel;
retrieving two or more scoreboard values from the scoreboard as source scoreboard values upon a determination that the instruction is not a one source instruction;
performing a logical operation on the two or more scoreboard values; and
storing a result of a logical operation in a destination address in the scoreboard as a destination scoreboard value; and
writing the first data in the first channel of the register file to the second channel upon a determination that the destination scoreboard value indicates that the two or more scoreboard values have the same value.

### Claim 6 (depends on 5)

The method of claim 5, further comprising executing all channels upon a determination that the destination scoreboard value indicates that the two or more scoreboard values have different values.