# US 10,769,546 B1 · Microwave integrated quantum circuits with cap wafer and methods for making the same

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- Number: US 10,769,546 B1
- Document ID: US10769546B1
- Status: Granted
- Kind: B1
- Application number: 16/113,382
- Filed: 2018-08-27
- Granted: 2020-09-08
- Earliest claimed: 2015-04-27
- Assignees: Rigetti & Co, LLC
- Applicants: Rigetti & Co, Inc.
- Inventors: Chad Tyler Rigetti; Dane Christoffer Thompson; Alexei N. Marchenkov; Mehrnoosh Vahidpour; Eyob A. Sete; Jean-Luc Francois-Xavier Orgiazzi
- Web page: https://patentgrep.com/patent/US10769546B1

## CPC

- G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
- G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- H10N 60/12: Josephson-effect devices
- H10N 60/815: {for Josephson-effect devices}
- H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/064: {by modifying the conductivity of conductive parts, e.g. by alloying}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 90/00: Package configurations
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07554: {changes in dispositions}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10S 977/933: Spintronics or quantum computing
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.

## Claims

### Claim 1

A quantum computing system comprising:
a first substrate having on a first surface one or more recesses, standoff bumps, an electrically conducting layer that conforms to the one or more recesses and the standoff bumps, and bonding elements coupled with the electrically conducting layer, the bonding elements being disposed outside the one or more recesses;
a second substrate having a first surface; and
one or more quantum circuit devices disposed on the first surface of the second substrate;
wherein the first substrate and the second substrate are bonded such that the one or more recesses form enclosures that respectively house the one or more quantum circuit devices.

### Claim 2 (depends on 1)

The quantum computing system of claim 1, wherein each of the one or more quantum circuit devices is one of a qubit, a tunable quantum coupler, a readout circuit including one or more linear resonators or one or more non-linear resonators, a filter, a quantum amplifier, or a circulator.

### Claim 3 (depends on 1)

The quantum computing system of claim 1,
wherein the bonding elements form an electromagnetic contact between the electrically conducting layer and structures of the second substrate that are grounded during operation of the quantum computing system.

### Claim 4 (depends on 3)

The quantum computing system of claim 3, wherein the one or more recesses of the first substrate isolate quantum circuit devices from interacting with spurious modes and surface loss to improve coherence times of the quantum circuit devices.

### Claim 5 (depends on 3)

The quantum computing system of claim 3, wherein the one or more recesses of the first substrate provide controlled coupling between neighboring quantum circuit devices.

### Claim 6 (depends on 3)

The quantum computing system of claim 3, wherein the one or more recesses of the first substrate reduce cross couplings between quantum circuit devices.

### Claim 7 (depends on 1)

The quantum computing system of claim 1, wherein the second substrate comprises one of silicon, sapphire, silicon oxide, silicon nitride, quartz, lithographically defined thick photoresists (SU8) or an electrical conducting material that is a superconducting material when the quantum computing system is operated.

### Claim 8 (depends on 1)

The quantum computing system of claim 1, wherein the bonding elements form an electromagnetic contact between the bonded first and second substrates through which the one or more quantum circuit devices disposed on the second substrate receive DC signals or MW signals from signal lines of the first substrate.

### Claim 9 (depends on 1)

The quantum computing system of claim 1, wherein the bonding elements comprise bumps that include an electrically conducting material that is a superconducting material when the quantum computing system is operated.

### Claim 10 (depends on 9)

The quantum computing system of claim 9, wherein the electrically conducting material is selected from the group consisting of indium, aluminum, and palladium.

### Claim 11 (depends on 9)

The quantum computing system of claim 9, wherein the bumps are arranged to form channels that allow for gas trapped between the bumps to be pumped out.

### Claim 12 (depends on 9)

The quantum computing system of claim 9, further comprising:
bond pads disposed on the first surface of the second substrate opposing the bumps.

### Claim 13 (depends on 12)

The quantum computing system of claim 12, wherein the bond pads comprise one of aluminum, indium, or titanium.

### Claim 14 (depends on 12)

The quantum computing system of claim 12, wherein the bond pads comprise a cap layer of one of aluminum, indium, or titanium.

### Claim 15 (depends on 1)

The quantum computing system of claim 1, wherein the standoff bumps include one of silicon oxide or silicon nitride.

### Claim 16 (depends on 1)

The quantum computing system of claim 1, wherein the standoff bumps form a non-hermetic connection between the first and second substrates that allows for gas trapped inside the one or more recesses of the first substrate to be pumped out.

### Claim 17

A method of fabricating a quantum computing system, the method comprising:
forming standoff bumps on a surface of a substrate;
etching one or more recesses in the surface of the substrate;
forming an electrically conducting layer that conforms to the standoff bumps and the one or more recesses;
forming bonding elements coupled with the electrically conducting layer, the bonding elements being formed outside the one or more recesses;
forming one or more quantum circuit devices on a first surface of a second substrate; and
bonding the substrate and the second substrate such that the one or more recesses form respective enclosures that house the one or more quantum circuit devices.

### Claim 18 (depends on 17)

The method of claim 17, wherein the etching of the recesses of the substrate is performed using either Deep Reactive Ion Etch process or a wet etch process with lithographic mask or machining.

### Claim 19 (depends on 17)

The method of claim 17, wherein the etching of the recesses of the substrate is performed to at least one specified depth using at least one lithographic mask and at least one etch stop layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein the at least one etch stop layer comprises one of Silicon Oxide, Silicon Nitride, or Aluminum oxide.

### Claim 21 (depends on 17)

The method of claim 17, wherein one or more of the forming operations are performed using a lithographic mask comprising one of photoresist, silicon oxide, or silicon nitride.

### Claim 22 (depends on 17)

The method of claim 17, wherein the forming of the electrically conducting layer is performed by sputtering, e beam evaporation, atomic layer deposition (ALD), Metal Organic Chemical Vapor Deposition (MOCVD) or electroplating.

### Claim 23 (depends on 17)

The method of claim 17, wherein the standoff bumps are thermally grown or deposited using one of low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

### Claim 24 (depends on 17)

The method of claim 17, further comprising:
depositing an adhesion layer on the electrically conducting layer,
wherein the bonding elements are formed on the adhesion layer.

### Claim 25 (depends on 24)

The method of claim 24, wherein the adhesion layer comprises an electrically conducting material that is a superconducting material when the quantum computing system is operated.

### Claim 26 (depends on 25)

The method of claim 25, wherein the electrically conducting material of the adhesion layer comprises one of titanium, or tantalum.

### Claim 27 (depends on 24)

The method of claim 24, wherein the adhesion layer is deposited by one of sputtering, evaporation, or electroplating.

### Claim 28 (depends on 17)

The method of claim 17, wherein the bonding elements are formed via one of sputtering, evaporation, or electroplating.

### Claim 29 (depends on 17)

The method of claim 17, wherein the bonding elements are formed to be longer than the standoff bumps.

### Claim 30 (depends on 29)

The method of claim 29, wherein the bonding elements are formed using one of lift-off resist, spray on resist, wet or dry etching.

### Claim 31 (depends on 17)

The method of claim 17, wherein the bonding of the substrate and the second substrate is performed by applying pressure on one or both of the substrates to be bonded.

### Claim 32 (depends on 31)

The method of claim 31, wherein the standoff bumps form a gap between the substrates to be bonded to control a bonding force.

### Claim 33 (depends on 31)

The method of claim 31, wherein a die bonder or a wafer bonder is used to align and bond the substrates to be bonded.

### Claim 34 (depends on 31)

The method of claim 31, further comprising:
dispersing nanoparticles over the bonding elements to break the oxide layers from the substrates.

### Claim 35 (depends on 34)

The method of claim 34, wherein the nanoparticles comprise diamond.

### Claim 36 (depends on 34)

The method of claim 34, wherein the nanoparticles have sharp edges to break oxide layers of the bonding elements.

### Claim 37 (depends on 34)

The method of claim 34, wherein the dispersing of the nanoparticles is performed by submersing the bonding elements in a solution containing the nanoparticles.

### Claim 38 (depends on 17)

The method of claim 17, wherein the bonding results in a low DC-resistance contact between the bonded substrates.