# US 10,769,526 B2 · Machine learning accelerator architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,526 B2 - Document ID: US10769526B2 - Status: Granted - Kind: B2 - Application number: 15/960,851 - Filed: 2018-04-24 - Published: 2019-10-24 - Granted: 2020-09-08 - Earliest claimed: 2018-04-24 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Bharat Daga; Pradeep Janedula; Aravind Babu Srinivasan; Ambili Vengallur - Web page: https://patentgrep.com/patent/US10769526B2 ## CPC - G06N 3/08: Learning methods - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06N 3/0442: characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/048: Activation functions - G06N 3/0495: Quantised networks; Sparse networks; Compressed networks - G06N 3/063: using electronic means - G06N 3/084: Backpropagation, e.g. using gradient descent - G06N 3/098: Distributed learning, e.g. federated learning - G06N 3/0475: Generative networks - G06N 3/088: Non-supervised learning, e.g. competitive learning - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises accelerator circuitry including a first set of processing elements to perform first computations including matrix multiplication operations, a second set of processing elements to perform second computations including sum of elements of weights and offset multiply operations and a third set of processing elements to perform third computations including sum of elements of inputs and offset multiply operations, wherein the second and third computations are performed in parallel with the first computations. ## Claims ### Claim 1 An apparatus to facilitate acceleration of machine learning operations, comprising accelerator circuitry, including: a first set of processing elements to perform first computations including matrix multiplication operations; a second set of processing elements to perform second computations including sum of elements of weights and offset multiply operations; and a third set of processing elements to perform third computations including sum of elements of inputs and offset multiply operations, wherein the second and third computations are performed in parallel with the first computations. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising a weights buffer coupled to the second set of processing elements to provide weight values to the second set of processing elements. ### Claim 3 (depends on 2) The apparatus of claim 2, further comprising an input buffer coupled to the third set of processing elements to provide input values to the third set of processing elements. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein results of the second and third computations are transmitted to the first set of processing elements. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the first set of processing elements computes a final result based on the results of the first, second and third computations and a constant value. ### Claim 6 (depends on 5) The apparatus of claim 5, further comprising post processor circuitry to perform a quantization operation on the final result. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the post processor circuitry further to perform one or more machine learning layer operations on the final result received from the first set of processing elements. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the one or more machine learning layer operations comprises rectified linear unit (ReLU) operations. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the ReLU operations are fused with the final result. ### Claim 10 A method to facilitate acceleration of machine learning operations, comprising: performing first computations including matrix multiplication operations at a first set of processing elements; performing second computations including sum of elements of weights and offset multiply operations at a second set of processing elements; and performing third computations including sum of elements of inputs and offset multiply operations at a third set of processing elements, wherein the second and third computations are performed in parallel with the first computations. ### Claim 11 (depends on 10) The method of claim 10, further comprising receiving weight values at the second set of processing elements prior to performing the second computations. ### Claim 12 (depends on 11) The method of claim 11, further comprising receiving input values at the third set of processing elements prior to performing the third computations. ### Claim 13 (depends on 12) The method of claim 12, further comprising receiving results of the second and third computations at the first set of processing elements. ### Claim 14 (depends on 13) The method of claim 13 further comprising computing a final result at the first set of processing elements based on the results of the first, second and third computations and a constant value. ### Claim 15 (depends on 14) The method of claim 14, further comprising performing a quantization operation on the final result at the first set of processing elements. ### Claim 16 (depends on 14) The method of claim 14, further comprising performing one or more machine learning layer operations on the final result received from the first set of processing elements. ### Claim 17 (depends on 16) The method of claim 16, wherein the one or more machine learning layer operations comprises rectified linear unit (ReLU) operations. ### Claim 18 (depends on 17) The method of claim 17, further comprising fusing the ReLU operations with the final result. ### Claim 19 An accelerator comprising: a plurality of tiles comprising a plurality of processing elements, including: a first tile having a first set of processing elements to perform first computations including matrix multiplication operations; a second tile having: a second set of processing elements to perform second computations including sum of elements of weights and offset multiply operations; and a third set of processing elements to perform third computations including sum of elements of inputs and offset multiply operations, wherein the second and third computations are performed in parallel with the first computations. ### Claim 20 (depends on 19) The accelerator of claim 19, wherein the second tile further comprises: a weights buffer coupled to the second set of processing elements to provide weight values to the second set of processing elements; and an input buffer coupled to the third set of processing elements to provide input values to the third set of processing elements. ### Claim 21 (depends on 20) The accelerator of claim 20, wherein results of the second and third computations are transmitted to the first set of processing elements, and wherein the first set of processing elements computes a final result based on the results of the first, second and third computations and a constant value. ### Claim 22 (depends on 21) The accelerator of claim 21, further comprising post processor circuitry to perform one or more machine learning layer operations on the final result received from the first set of processing elements.