# US 10,769,520 B2 · Semiconductor device and system using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,520 B2 - Document ID: US10769520B2 - Status: Granted - Kind: B2 - Application number: 16/826,871 - Filed: 2020-03-23 - Published: 2020-07-23 - Granted: 2020-09-08 - Earliest claimed: 2016-03-18 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Yoshiyuki Kurokawa - Web page: https://patentgrep.com/patent/US10769520B2 ## CPC - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G06N 3/0499: Feedforward networks - G06N 3/063: using electronic means - G06N 3/065: Analogue means - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/16: Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - G06N 3/045: Combinations of networks - G11C 11/403: with charge regeneration common to a multiplicity of memory cells, i.e. external refresh - G11C 2207/104: Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs - G11C: STATIC STORES (semiconductor memory devices H10B) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained. ## Claims ### Claim 1 A semiconductor device comprising: an artificial neural network comprising a product-sum operation circuit, wherein the product-sum operation circuit comprises a first memory cell, a second memory cell, and an offset circuit, wherein the first memory cell is configured to store a first analog data, wherein the second memory cell is configured to store a reference analog data, wherein the first memory cell and the second memory cell are configured to supply a first current and a second current, respectively, when a reference potential is applied as a selection signal, wherein the offset circuit is configured to supply a third current corresponding to a differential current between the first current and the second current to the first memory cell, wherein the first memory cell and the second memory cell are configured to supply a fourth current and a fifth current, respectively, when a potential corresponding to a second analog data is applied as the selection signal, and wherein the product-sum operation circuit is configured to obtain a current that depends on the sum of products of the first analog data and the second analog data by subtracting the third current from a differential current between the fourth current and the fifth current. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the offset circuit comprises a first constant current circuit, a second constant current circuit, first to third transistors, a first capacitor, a first wiring, a second wiring, a first output terminal, a second output terminal, and a current mirror circuit, wherein the first constant current circuit is electrically connected to the first wiring, wherein a first terminal of the first transistor is electrically connected to a first terminal of the second transistor, wherein a gate of the first transistor is electrically connected to a second terminal of the second transistor, wherein the first terminal of the second transistor is electrically connected to the first wiring, wherein a first terminal of the third transistor is electrically connected to the second terminal of the second transistor, wherein a first terminal of the first capacitor is electrically connected to the gate of the first transistor, wherein the first wiring is electrically connected to the first output terminal, wherein the second constant current circuit is electrically connected to the second wiring, wherein the second wiring is electrically connected to the second output terminal, wherein the current mirror circuit is configured to output a current corresponding to a potential of the second wiring from the first wiring and the second wiring, wherein the first memory cell is electrically connected to the first output terminal, and wherein the second memory cell is electrically connected to the second output terminal. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the first constant current circuit comprises a fourth transistor, wherein the second constant current circuit comprises a fifth transistor, wherein the fourth transistor and the fifth transistor each comprise a back gate, wherein a first terminal of the fourth transistor is electrically connected to the first wiring, wherein a gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor, wherein a first terminal of the fifth transistor is electrically connected to the second wiring, and wherein a gate of the fifth transistor is electrically connected to the first terminal of the fifth transistor. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the current mirror circuit comprises a sixth transistor and a seventh transistor, wherein a first terminal of the sixth transistor is electrically connected to the first wiring, wherein a gate of the sixth transistor is electrically connected to the second wiring, wherein a first terminal of the seventh transistor is electrically connected to the second wiring, and wherein a gate of the seventh transistor is electrically connected to the second wiring. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein the first memory cell comprises an eighth transistor, a ninth transistor, and a second capacitor, wherein the second memory cell comprises a tenth transistor, an eleventh transistor, and a third capacitor, wherein a first terminal of the eighth transistor is electrically connected to a gate of the ninth transistor, wherein a first terminal of the second capacitor is electrically connected to the first terminal of the eighth transistor, wherein a first terminal of the ninth transistor is electrically connected to the first output terminal, wherein a first terminal of the tenth transistor is electrically connected to a gate of the eleventh transistor, wherein a first terminal of the third capacitor is electrically connected to the first terminal of the tenth transistor, and wherein a first terminal of the eleventh transistor is electrically connected to the second output terminal. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the first to eleventh transistors each have a same polarity. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein at least one of channel formation regions in the first to eleventh transistors comprises an oxide containing at least one of indium, an element M, and zinc, and wherein the element M is any one of aluminum, gallium, yttrium, and tin. ### Claim 8 (depends on 1) An electronic device comprising: the semiconductor device according to claim 1; and a housing. ### Claim 9 (depends on 1) An electronic device comprising: the semiconductor device according to claim 1 and is configured to perform processing such as pattern recognition and associative storage.