# US 10,769,513 B2 · Device and method for managing the current consumption of an integrated module

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- Number: US 10,769,513 B2
- Document ID: US10769513B2
- Status: Granted
- Kind: B2
- Application number: 16/227,525
- Filed: 2018-12-20
- Published: 2019-04-25
- Granted: 2020-09-08
- Earliest claimed: 2017-01-03
- Assignees: STMicroelectronics (Rousset) SAS
- Applicants: STMicroelectronics (Rousset) SAS
- Inventors: Alexandre Sarafianos; Thomas Ordas; Yanis Linge; Jimmy Fort
- Web page: https://patentgrep.com/patent/US10769513B2

## CPC

- G06K 19/07363: {by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis}
- G06F 21/445: {by mutual authentication, e.g. between devices or programs}
- G06F 21/75: by inhibiting the analysis of circuitry or operation
- G06F 21/755: {with measures against power attack}
- H10W 42/405: {using active circuits}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

## Claims

### Claim 1

A method for managing current consumption of a logic circuit coupled between a first supply terminal and a second supply terminal, the method comprising:
receiving an input signal at an input terminal of the logic circuit;
producing an output signal at an output terminal of the logic circuit;
at a first time, causing the output signal to transition from a first state to a second state while generating an additional current between the first supply terminal and the second supply terminal; and
at a second time, causing the output signal to transition from the first state to the second state without generating the additional current.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
receiving a control signal; and
determining whether to generate the additional current during a transition from the first state to the second state based on the control signal.

### Claim 3 (depends on 2)

The method of claim 2, wherein the control signal is a pseudorandom signal.

### Claim 4 (depends on 2)

The method of claim 2, further comprising determining whether the additional current comprises a first current peak or a second current peak based on the control signal, wherein the second current peak is different than the first current peak.

### Claim 5 (depends on 2)

The method of claim 2, wherein generating the additional current comprises:
controlling a first auxiliary transistor with the output signal;
controlling a second auxiliary transistor with the control signal; and
controlling a third auxiliary transistor with the input signal.

### Claim 6 (depends on 5)

The method of claim 5, wherein the third auxiliary transistor is coupled between the first auxiliary transistor and the second auxiliary transistor.

### Claim 7 (depends on 5)

The method of claim 5, wherein the first, second, and third auxiliary transistors are coupled in series.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first state is a high state and the second state is a low state.

### Claim 9 (depends on 8)

The method of claim 8, wherein the high state corresponds to a voltage of about 3 V, and the low state corresponds to a voltage of about 0 V.

### Claim 10 (depends on 1)

The method of claim 1, wherein the logic circuit comprises an inverter, a NAND gate, or a NOR gate.

### Claim 11 (depends on 1)

The method of claim 1, wherein the logic circuit comprises a latch.

### Claim 12 (depends on 1)

The method of claim 1, wherein the logic circuit comprises shift register.

### Claim 13

A method for managing current consumption of a logic circuit coupled between a first supply terminal and a second supply terminal, the method comprising:
receiving an input signal at an input terminal of the logic circuit;
producing an output signal at an output terminal of the logic circuit;
receiving a control signal; and
generating an additional current between the first supply terminal and the second supply terminal each time the output signal transitions from a first state to a second state, wherein a magnitude of the additional current is based on the control signal.

### Claim 14 (depends on 13)

The method of claim 13, wherein the control signal is a pseudorandom signal.

### Claim 15

A circuit comprising:
a logic circuit coupled between a first supply terminal and a second supply terminal and comprising an input terminal configured to receive an input signal, and an output terminal configured to produce an output signal; and
an auxiliary circuit coupled between the first supply terminal and the second supply terminal and comprising an input terminal configured to receive a control signal, the auxiliary circuit configured to generate an additional current between the first supply terminal and the second supply terminal when the output signal transitions from a first state to a second state, wherein a magnitude of the additional current is based on the control signal.

### Claim 16 (depends on 15)

The circuit of claim 15, wherein the logic circuit comprises an inverter, a NAND gate, or a NOR gate.

### Claim 17 (depends on 15)

The circuit of claim 15, wherein the logic circuit comprises:
a first inverter having an input terminal coupled to the input terminal of the logic circuit, and an output terminal coupled to the output terminal of the logic circuit; and
a second inverter having an input terminal coupled to the output terminal of the first inverter, and an output terminal coupled to the input terminal of the first inverter.

### Claim 18 (depends on 17)

The circuit of claim 17, wherein the auxiliary circuit is further configured to generate a second additional current between the first supply terminal and the second supply terminal based on the control signal when an output signal of the second inverter transitions from the first state to the second state.

### Claim 19 (depends on 17)

The circuit of claim 17, wherein the auxiliary circuit is further configured to generate a second additional current between the first supply terminal and the second supply terminal based on a second control signal different from the control signal when an output signal of the second inverter transitions from the first state to the second state.

### Claim 20 (depends on 19)

The circuit of claim 19, wherein the control signal and the second control signal are pseudorandom signals.

### Claim 21 (depends on 17)

The circuit of claim 17, wherein the first inverter and the second inverter are part of a shift register.