# US 10,769,340 B2 · Automatic moving of probe locations for parasitic extraction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,340 B2 - Document ID: US10769340B2 - Status: Granted - Kind: B2 - Application number: 16/411,209 - Filed: 2019-05-14 - Published: 2019-11-21 - Granted: 2020-09-08 - Earliest claimed: 2018-05-16 - Assignees: Mentor Graphics Corporation - Applicants: Mentor Graphics Corporation - Inventors: Sridhar Srinivasan; Yi-Ting Lee; Patrick D. Gibson; Padmaja Susarla; Alex Thompson - Web page: https://patentgrep.com/patent/US10769340B2 ## CPC - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted. ## Claims ### Claim 1 A method, executed by at least one processor of a computer, comprising: identifying probe location candidates for parasitic extraction from geometric elements on a probe layer, the probe layer being a physical layer of a layout design for a circuit design predetermined for placing one or more new probes, the probe location candidates being geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value, the probe location candidates being conductively connected to the original probe location, and the original probe location being on a geometric element representing a device pin of the circuit design on another physical layer; selecting one or more new probe locations on the probe location candidates based on predetermined criteria; and extracting, from the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations. ### Claim 2 (depends on 1) The method recited in claim 1, further comprising: conducting an ESD analysis based on the parasitic resistance value; and reporting the parasitic resistance value, the result of the ESD analysis, or both. ### Claim 3 (depends on 1) The method recited in claim 1, wherein the original probe location is an electrode of a diode, the probe layer is a diffusion layer, and the probe location candidates comprise a guard ring for the diode. ### Claim 4 (depends on 1) The method recited in claim 1, where the original probe location is a gate electrode of a transistor and the probe layer is a metal layer. ### Claim 5 (depends on 1) The method recited in claim 1, wherein the area forms a halo surrounding a location on the probe layer corresponding to the original probe location. ### Claim 6 (depends on 1) The method recited in claim 1, wherein the predetermined criteria comprise distance from the original probe location, distance between the one or more new probe locations, configuration of the one or more new probe locations, or any combination thereof. ### Claim 7 One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: identifying probe location candidates for parasitic extraction from geometric elements on a probe layer, the probe layer being a physical layer of a layout design for a circuit design predetermined for placing one or more new probes, the probe location candidates being geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value, the probe location candidates being conductively connected to the original probe location, and the original probe location being on a geometric element representing a device pin of the circuit design on another physical layer; selecting one or more new probe locations on the probe location candidates based on predetermined criteria; and extracting, from the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations. ### Claim 8 (depends on 7) The one or more non-transitory computer-readable media recited in claim 7, wherein the method further comprises: conducting an ESD analysis based on the parasitic resistance value; and reporting the parasitic resistance value, the result of the ESD analysis, or both. ### Claim 9 (depends on 7) The one or more non-transitory computer-readable media recited in claim 7, wherein the original probe location is an electrode of a diode, the probe layer is a diffusion layer, and the probe location candidates comprise a guard ring for the diode. ### Claim 10 (depends on 7) The one or more non-transitory computer-readable media recited in claim 7, where the original probe location is a gate electrode of a transistor and the probe layer is a metal layer. ### Claim 11 (depends on 7) The one or more non-transitory computer-readable media recited in claim 7, wherein the area forms a halo surrounding a location on the probe layer corresponding to the original probe location. ### Claim 12 (depends on 7) The one or more non-transitory computer-readable media recited in claim 7, wherein the predetermined criteria comprise distance from the original probe location, distance between the one or more new probe locations, configuration of the one or more new probe locations, or any combination thereof. ### Claim 13 A method, executed by at least one processor of a computer, comprising: selecting a cell port of a first cell conductively connected to an original probe location as a new probe location, the original probe location being on a geometric element representing a device pin of the circuit design on a physical layer of a layout design of a circuit design or a cell port of a second cell, the second cell being inside the first cell; and extracting, from the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new probe location. ### Claim 14 (depends on 13) The method recited in claim 13, wherein the method further comprises: conducting an ESD analysis based on the parasitic resistance value; and reporting the parasitic resistance value, the result of the ESD analysis, or both. ### Claim 15 One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: selecting a cell port of a first cell conductively connected to an original probe location as a new probe location, the original probe location being on a geometric element representing a device pin of the circuit design on a physical layer of a layout design of a circuit design or a cell port of a second cell, the second cell being inside the first cell; and extracting, from the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new probe location. ### Claim 16 (depends on 15) The one or more non-transitory computer-readable media recited in claim 15, wherein the method further comprises: conducting an ESD analysis based on the parasitic resistance value; and reporting the parasitic resistance value, the result of the ESD analysis, or both.