# US 10,769,334 B2 · Intelligent fail recognition > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,334 B2 - Document ID: US10769334B2 - Status: Granted - Kind: B2 - Application number: 16/193,598 - Filed: 2018-11-16 - Published: 2020-05-21 - Granted: 2020-09-08 - Earliest claimed: 2018-11-16 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Bryan G. Hickerson; Mohamed Baker Alawieh; Brian L. Kozitza; John R. Reysa; Erica Stuecheli - Web page: https://patentgrep.com/patent/US10769334B2 ## CPC - G06F 30/3323: using formal methods, e.g. equivalence checking or property checking - G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) - G06F 30/30: Circuit design - G06F 30/3308: using simulation - G06F 2115/10: Processors - G06N 20/00: Machine learning - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels. ## Claims ### Claim 1 A method of debugging one or more simulation fails in processor design verification, the method comprising: determining whether a prediction model to predict one or more bug labels for the one or more simulation fails in a processor design exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels for the one or more simulation fails in the processor design using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels in the processor design. ### Claim 2 (depends on 1) The method of claim 1, further comprising: determining whether the fix for the one or more predicted bug labels failed; and providing, in response to determining that the fix for the one or more predicted bug labels failed, the one or more predicted bug labels for review. ### Claim 3 (depends on 1) The method of claim 1, further comprising providing, in response to determining the fix is not available for the one or more predicted bug labels, the one or more predicted bug labels to a queue for processing in a training data store. ### Claim 4 (depends on 1) The method of claim 1, further comprising: retrieving, in response to determining the prediction model does not exist, a group of debugged and labeled bug instances, and determining whether a number of labeled bug instances in the group is greater than or equal to a threshold number. ### Claim 5 (depends on 4) The method of claim 4, further comprising storing, in response to determining that the number of labeled bug instances in the group is not greater than or equal to the threshold number, the group of debugged and labeled bug instances in storage as training data. ### Claim 6 (depends on 4) The method of claim 4, further comprising training the prediction model based on automated pre-processing and feature extraction. ### Claim 7 (depends on 4) The method of claim 4, further comprising training, in response to determining that the number of labeled bug instances in the group is greater than or equal to the threshold number, the prediction model. ### Claim 8 (depends on 1) The method of claim 1, wherein predicting one or more bug labels using the prediction model further comprises extracting features of a simulation file related to one or more bug instances of the simulation file and predicting one or more bug labels of one or more bug instances in the simulation file. ### Claim 9 A computer program product comprising: a non-transitory computer-readable storage medium having program instructions embodied therewith for debugging one or more simulation fails in processor design verification, the program instructions executable by one or more processors, the program instructions including: determining whether a prediction model to predict one or more bug labels for the one or more simulation fails in a processor design exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels for the one or more simulation fails in the processor design using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels in the processor design. ### Claim 10 (depends on 9) The computer program product of claim 9, wherein the program instructions further include: determining whether the fix for the one or more predicted bug labels failed; and providing, in response to determining that the fix for the one or more predicted bug labels failed, the one or more predicted bug labels for review. ### Claim 11 (depends on 9) The computer program product of claim 9, wherein the program instructions further include providing, in response to determining the fix is not available for the one or more predicted bug labels, the one or more predicted bug labels to a queue for processing in a training data store. ### Claim 12 (depends on 10) The computer program product of claim 10, wherein the program instructions further include determining whether a number of labeled bug instances in the group is greater than or equal to a threshold number. ### Claim 13 (depends on 12) The computer program product of claim 12, wherein the program instructions further include storing, in response to determining that the number of labeled bug instances in the group is not greater than or equal to the threshold number, the group of debugged and labeled bug instances in storage as training data. ### Claim 14 (depends on 12) The computer program product of claim 12, wherein the program instructions further include training, in response to determining that the number of labeled bug instances in the group is greater than or equal to the threshold number, the prediction model. ### Claim 15 A fail recognition apparatus for debugging one or more simulation fails in processor design verification, the fail recognition apparatus comprising: memory having program instructions embodied therewith, and at least one processor configured to read the program instructions to execute: a simulation environment configured to determine whether a prediction model to predict one or more bug labels for the one or more simulation fails in a processor exists; a model predictor configured to, in response to determining the prediction model exists, retrieve the prediction model and predict one or more bug labels for the one or more simulation fails in the processor design using the prediction model; and a feedback unit configured to determine whether a fix is available for the one or more predicted bug labels, and simulate, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels in the processor design. ### Claim 16 (depends on 15) The fail recognition apparatus of claim 15, wherein the feedback unit is further configured to determine whether the fix for the one or more predicted bug labels failed, and to provide in response to determining that the fix for the one or more predicted bug labels failed, the one or more predicted bug labels for review. ### Claim 17 (depends on 15) The fail recognition apparatus of claim 15, further comprising a model trainer configured to receive, in response to determining the prediction model does not exist, a group of debugged and labeled bug instances. ### Claim 18 (depends on 17) The fail recognition apparatus of claim 17, wherein the model trainer is further configured to determine whether a number of labeled bug instances in the group is greater than or equal to a threshold number. ### Claim 19 (depends on 18) The fail recognition apparatus of claim 18, wherein the model trainer is further configured to store, in response to determining that the number of labeled bug instances in the group is not greater than or equal to the threshold number, the group of debugged and labeled bug instances in storage as training data. ### Claim 20 (depends on 17) The fail recognition apparatus of claim 17, wherein the model trainer is further configured to train, in response to determining that the number of labeled bug instances in the group is greater than or equal to the threshold number, the prediction model.