# US 10,769,333 B1 · System, method, and computer program product for debugging one or more observable failures in a formal verification > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,333 B1 - Document ID: US10769333B1 - Status: Granted - Kind: B1 - Application number: 16/148,203 - Filed: 2018-10-01 - Granted: 2020-09-08 - Earliest claimed: 2018-10-01 - Assignees: Cadence Design Systems, Inc. - Applicants: Cadence Design Systems, Inc. - Inventors: Maayan Ziv; Nizar Hanna; Sanaa Halloun - Web page: https://patentgrep.com/patent/US10769333B1 ## CPC - G06F 30/3323: using formal methods, e.g. equivalence checking or property checking - G06F 30/30: Circuit design - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present disclosure relates to a method for electronic design verification. Embodiments may include providing, using a processor, an electronic design and determining one or more design violations based upon, at least in part, a structural observability filter. Embodiments may also include generating a violation trace based upon, at least in part, the one or more design violations and displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations. Embodiments may further include allowing the user to select at least one path to be waived at the graphical user interface and generating a new violation trace without the at least one path to be waived. ## Claims ### Claim 1 A computer-implemented method for electronic design verification comprising: providing, using a processor, an electronic design; determining one or more design violations based upon, at least in part, a structural observability filter; generating a violation trace based upon, at least in part, the one or more design violations, wherein the violation trace includes a violation starting point and at least one boundary signal; displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations; allowing the user to select at least one path to be waived at the graphical user interface; generating a new violation trace without the at least one path to be waived; and allowing the user to debug beginning at the boundary signal after the new violation trace without the at least one path to be waived is generated. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, further comprising: allowing the user to correct a violation at the graphical user interface. ### Claim 3 (depends on 1) The computer-implemented method of claim 1, wherein allowing the user to select at least one path to be waived at the graphical user interface includes a plurality of paths. ### Claim 4 (depends on 1) The computer-implemented method of claim 1, further comprising: displaying the at least one boundary signal at the graphical user interface. ### Claim 5 (depends on 1) The computer-implemented method of claim 1, further comprising: displaying at least a portion of the violation trace at the graphical user interface. ### Claim 6 A non-transitory computer-readable storage medium for electronic design verification, the computer-readable storage medium having stored thereon instructions that when executed by a machine result in one or more operations, the operations comprising: providing, using a processor, an electronic design; determining one or more design violations based upon, at least in part, a structural observability filter; generating a violation trace based upon, at least in part, the one or more design violations, wherein the violation trace includes a violation starting point and at least one boundary signal; displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations; allowing the user to select at least one path to be waived at the graphical user interface; generating a new violation trace without the at least one path to be waived; and allowing the user to debug beginning at the boundary signal after the new violation trace without the at least one path to be waived is generated. ### Claim 7 (depends on 6) The computer-readable storage medium of claim 6, further comprising: allowing the user to correct a violation at the graphical user interface. ### Claim 8 (depends on 6) The computer-readable storage medium of claim 6, wherein allowing the user to select at least one path to be waived at the graphical user interface includes a plurality of paths. ### Claim 9 (depends on 6) The computer-readable storage medium of claim 6, further comprising: displaying the at least one boundary signal at the graphical user interface. ### Claim 10 (depends on 6) The computer-readable storage medium of claim 6, further comprising: displaying at least a portion of the violation trace at the graphical user interface. ### Claim 11 A system for electronic design verification comprising: a computing device having at least one processor configured to provide an electronic design and determine one or more design violations based upon, at least in part, a structural observability filter, the at least one processor further configured to generate a violation trace based upon, at least in part, the one or more design violations, wherein the violation trace includes a violation starting point and at least one boundary signal, and to display the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations, the at least one processor further configured to allow the user to select at least one path to be waived at the graphical user interface and to generate a new violation trace without the at least one path to be waived, the at least one processor further configured to allow the user to debug beginning at the boundary signal after the new violation trace without the at least one path to be waived is generated. ### Claim 12 (depends on 11) The system of claim 11, further comprising: allowing the user to correct a violation at the graphical user interface. ### Claim 13 (depends on 11) The system of claim 11, wherein allowing the user to select at least one path to be waived at the graphical user interface includes a plurality of paths. ### Claim 14 (depends on 13) The system of claim 13, further comprising: displaying the at least one boundary signal at the graphical user interface.