# US 10,769,328 B2 · Generating a template-driven schematic from a netlist of electronic circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,328 B2 - Document ID: US10769328B2 - Status: Granted - Kind: B2 - Application number: 16/146,008 - Filed: 2018-09-28 - Published: 2019-04-04 - Granted: 2020-09-08 - Earliest claimed: 2017-09-30 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Pradeep Kumar Chawda; Makram Monzer Mansour - Web page: https://patentgrep.com/patent/US10769328B2 ## CPC - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 30/3308: using simulation - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 2111/12: Symbolic schematics - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Generating a template-driven schematic from a netlist of electronic circuits is disclosed. The template-driven schematic may be useful to generate a set of related circuits for a single overall design as well as allow for a common transfer mechanism between different Computer Aided Design (CAD) systems. To assist in portability of designs, a common file format is disclosed based on a structured text file (e.g., XML). Further, in the disclosed approach, it is possible to not only place primitives but create custom symbols as well. In addition, primitives and symbols may be attached to models, simulation settings may be added, and routing of the circuit in a schematic may be completed. Associated devices and methods are disclosed as well. ## Claims ### Claim 1 A computer system, comprising: a memory; and a processing device communicatively coupled to the memory, wherein the memory stores instructions that when executed by the processing device cause the processing device to: receive an indication to export information pertaining to a first electronic design from a first Electronic Design Automation (EDA) tool executing on the computer system, the indication to export comprising information to request export in a common file format, the common file format comprising a human readable text based common file format; export information describing the first electronic design from the first EDA tool; and store the export information in a first simulation exchange format (SEF) file describing the first electronic design in the common file format, wherein the common file format in the SEF file includes information sufficient to recreate the placement and routing of components in the first electronic design, the information in the SEF file comprising: a schematic element including a hierarchical description of at least one circuit block and leaf elements of the at least one circuit block, the leaf elements comprising circuit components in the schematic; a component model element including at least one model for the circuit components in the schematic description for use in simulations; a simulation setup element including information used to set up simulations of the components in the schematic; and a symbol information component including graphical information used to display symbols corresponding to circuit blocks and components in the schematic. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the SEF file in the common file format further includes sufficient information to perform at least one simulation of the first electronic design. ### Claim 3 (depends on 1) The computer system of claim 1, wherein common file format is stored in XML. ### Claim 4 (depends on 1) The computer system of claim 1, wherein exporting information describing the first electronic design from the first EDA tool is performed by interfacing with an Application Program Interface of the first EDA tool. ### Claim 5 (depends on 1) The computer system of claim 1, wherein exporting information describing the first electronic design from the first EDA tool is performed natively by the first EDA tool. ### Claim 6 (depends on 1) The computer system of claim 1, wherein the instructions further cause the processing device to generate a plurality of related SEF files based on the stored SEF file. ### Claim 7 (depends on 1) The computer system of claim 1, wherein a template is used for at least one component placement. ### Claim 8 (depends on 1) The computer system of claim 1, wherein the instructions further cause the processing device to: receive an indication to import, a second simulation exchange format (SEF) file defining a second electronic design, to the first Electronic Design Automation (EDA) tool, the second SEF file comprising information sufficient to recreate the placement and routing of components in the second electronic design; process the second SEF file to identify component objects and associate model names to the identified component objects; process the second SEF file to map components to a symbol and obtain location, rotation, and mirroring information pertaining to the symbol; process the second SEF file to place components and route wires between components based on at least one constraint; and present a schematic view of the second electronic design in the first EDA tool. ### Claim 9 (depends on 1) The computer system of claim 1, wherein the instructions further cause the processing device to: receive an indication to import, the first simulation exchange format (SEF) file defining the first electronic design, to a second Electronic Design Automation (EDA) tool executing on the computer system, the second SEF file comprising information sufficient to recreate the placement and routing of components in the first electronic design; process the first SEF file to identify component objects and associate model names to the identified component objects; process the first SEF file to map components to a symbol and obtain location, rotation, and mirroring information pertaining to the symbol; process the first SEF file to place components and route wires between components based on at least one constraint; and present a schematic view of the first electronic design in the second EDA tool. ### Claim 10 (depends on 9) The computer system of claim 9, wherein at least a portion of the information pertaining to the second electronic design is decrypted from the first SEF file. ### Claim 11 (depends on 1) The computer system of claim 1, wherein at least a portion of the information pertaining to the first electronic design is encrypted prior to storing in the first SEF file. ### Claim 12 A computer system, comprising: a memory; and a processing device communicatively coupled to the memory, wherein the memory stores instructions that when executed by the processing device cause the processing device to: receive an indication to import, a simulation exchange format (SEF) file defining an electronic design in a human readable text based common file format, to a first Electronic Design Automation (EDA) tool executing on the computer system, the SEF file comprising information sufficient to recreate the placement and routing of components in the electronic design, the information in the SEF file comprising: a schematic element including a hierarchical description of at least one circuit block and leaf elements of the at least one circuit block, the leaf elements comprising circuit components in the schematic; a component model element including at least one model for the circuit components in the schematic description for use in simulations; a simulation setup element including information used to set up simulations of the components in the schematic; and a symbol information component including graphical information used to display symbols corresponding to circuit blocks and components in the schematic; process the SEF file to identify component objects and associate model names to the identified component objects; process the SEF file to map components to a symbol and obtain location, rotation, and mirroring information pertaining to the symbol; process the SEF file to place components and route wires between components based on at least one constraint; and present a schematic view of the electronic design in the first EDA tool. ### Claim 13 (depends on 12) The computer system of claim 12, wherein the instructions further cause the processing device to process the SEF file to identify simulation information for the electronic design. ### Claim 14 (depends on 13) The computer system of claim 13, wherein the instructions further cause the processing device to: receive an indication to initiate a simulation on the electronic design; and provide simulation results based, in part, on simulation settings obtained from the SEF file. ### Claim 15 A non-transitory computer readable medium comprising instructions stored thereon that when executed by a processing device cause the processing device to: receive an indication to export information pertaining to a first electronic design from a first Electronic Design Automation (EDA) tool executing on the computer system, the indication to export comprising information to request export in a human readable text based common file format; exporting information describing the first electronic design from the first EDA tool; and store the information in a first simulation exchange format (SEF) file describing the first electronic design in the common file format, wherein the SEF file in the common file format includes information sufficient to recreate the placement and routing of components in the first electronic design, the information in the SEF file comprising: a schematic element including a hierarchical description of at least one circuit block and leaf elements of the at least one circuit block, the leaf elements comprising circuit components in the schematic; a component model element including at least one model for the circuit components in the schematic description for use in simulations; a simulation setup element including information used to set up simulations of the components in the schematic; and a symbol information component including graphical information used to display symbols corresponding to circuit blocks and components in the schematic. ### Claim 16 (depends on 15) The non-transitory computer readable medium of claim 15, wherein the SEF file in the common file format further includes sufficient information to perform at least one simulation of the first electronic design. ### Claim 17 (depends on 15) The non-transitory computer readable medium of claim 15, wherein common file format is stored in XML. ### Claim 18 (depends on 16) The non-transitory computer readable medium of claim 16, further comprising instructions to cause the processing device to: receive an indication to import, a second simulation exchange format (SEF) file defining a second electronic design, to the first Electronic Design Automation (EDA) tool, the second SEF file comprising information sufficient to recreate the placement and routing of components in the second electronic design; process the second SEF file to identify component objects and associate model names to the identified component objects; process the second SEF file to map components to a symbol and obtain location, rotation, and mirroring information pertaining to the symbol; process the second SEF file to place components and route wires between components based on at least one constraint; and present a schematic view of the second electronic design in the first EDA tool. ### Claim 19 (depends on 18) The non-transitory computer readable medium of claim 18, further comprising instructions to cause the processing device to: receive an indication to import, the first simulation exchange format (SEF) file defining the first electronic design, to a second Electronic Design Automation (EDA) tool executing on the computer system; process the first SEF file to identify component objects and associate model names to the identified component objects; process the first SEF file to map components to a symbol and obtain location, rotation, and mirroring information pertaining to the symbol; process the first SEF file to place components and route wires between components based on at least one constraint; and present a schematic view of the first electronic design in the second EDA tool. ### Claim 20 (depends on 19) The non-transitory computer readable medium of claim 19, wherein at least a portion of the information pertaining to the second electronic design is decrypted from the first SEF file.