# US 10,769,327 B1 · Integrated circuit authentication using mask fingerprinting > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,327 B1 - Document ID: US10769327B1 - Status: Granted - Kind: B1 - Application number: 16/440,295 - Filed: 2019-06-13 - Granted: 2020-09-08 - Earliest claimed: 2019-06-13 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Effendi Leobandung - Web page: https://patentgrep.com/patent/US10769327B1 ## CPC - H04L 41/147: for predicting network behaviour - G06F 30/30: Circuit design - H04L 41/0806: for initial configuration or provisioning, e.g. plug-and-play - H04L 41/0895: Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements - H04L 41/149: for prediction of maintenance - H04L 41/40: using virtualisation of network functions or resources, e.g. SDN or NFV entities - H04L 41/145: {involving simulating, designing, planning or modelling of a network} - H04L 41/5054: Automatic deployment of services triggered by the service manager, e.g. service implementation by automatic configuration of network components - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for fabricating a semiconductor chip includes controlling a chip testing device to measure, for each bit of a plurality of bits in the semiconductor chip, mask dimensions for a feature to determine variations of the feature within each bit. Based on the variations a probability of each bit being “0” or “1” is generated to provide predicated probabilities. Based on the predicted probabilities, each bit of the plurality of bits is grouped and a subset of bits is selected to provide a subset of predicted results. The chip testing unit is controlled to measure whether each bit of the subset of bits is in a state is “0” or “1” to provide measured results. The subset of predicted results is compared with the measured results to provide a comparison. Based on the comparison, determination is made that the semiconductor chip has been fabricated using an altered mask. ## Claims ### Claim 1 A computer-implemented method for authenticating a semiconductor chip, the computer-implemented method comprising: controlling, using a processor, a chip testing unit to measure, for each bit of a plurality of bits in the semiconductor chip, mask dimensions for a feature to determine variations of the feature within each bit; using the processor to predict based on the variations, for each bit of the plurality of bits, a probability of being “0” or “1” to provide predicated probabilities; using the processor to group, based on the predicted probabilities, each bit of the plurality of bits and selecting a subset of bits to provide a subset of predicted results; controlling, using the processor, the chip testing unit to measure each bit of the subset of bits is in a state is “0” or “1” to provide measured results; using the processor to compare the subset of predicted results and the measured results to provide a comparison; and using the processor to determine, based on the comparison, that the semiconductor chip has been fabricated using an altered mask. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, wherein the plurality of bits comprises a static random access memory cell. ### Claim 3 (depends on 1) The computer-implemented method of claim 1, wherein the feature comprises a gate mask dimension. ### Claim 4 (depends on 1) The computer-implemented method of claim 1, wherein the feature comprises a gate dimension over an active area. ### Claim 5 (depends on 1) The computer-implemented method of claim 1, wherein the feature comprises a via dimension. ### Claim 6 (depends on 1) The computer-implemented method of claim 1, wherein the feature comprises a metal feature dimension. ### Claim 7 (depends on 1) The computer-implemented method of claim 1, wherein selecting the subset of bits comprises selecting a group of bits with at least 65% probability of being either “0” or “1.” ### Claim 8 A system for authenticating a semiconductor chip, the system comprising: a processor in communication with one or more types of memory, the processor configured to: control a chip testing unit to measure, for each bit of a plurality of bits in the semiconductor chip, mask dimensions for a feature to determine variations of the feature within each bit; predict based on the variations, for each bit of the plurality of bits, a probability of being “0” or “1” to provide predicated probabilities; group, based on the predicted probabilities, each bit of the plurality of bits and select a subset of bits to provide a subset of predicted results; control the chip testing unit to measure each bit of the subset of bits is in a state is “0” or “1” to provide measured results; compare the subset of predicted results to the measured results to provide a comparison; and determine, based on the comparison, that the semiconductor chip has been fabricated using an altered mask. ### Claim 9 (depends on 8) The system of claim 8, wherein the plurality of bits comprises a static random access memory cell. ### Claim 10 (depends on 8) The system of claim 8, wherein the feature comprises a gate mask dimension. ### Claim 11 (depends on 8) The system of claim 8, wherein the feature comprises a gate dimension over an active area. ### Claim 12 (depends on 8) The system of claim 8, wherein the feature comprises a via dimension. ### Claim 13 (depends on 8) The system of claim 8, wherein the feature comprises a metal feature dimension. ### Claim 14 (depends on 8) The system of claim 8, wherein selecting the subset of bits comprises selecting a group of bits with at least 65% probability of being either “0” or “1.” ### Claim 15 A computer program product for authenticating a semiconductor chip, the computer program product comprising: a computer readable storage medium readable by a processing circuit and storing program instructions for execution by the processing circuit for performing a method comprising: controlling, using a processor, a chip testing unit to measure, for each bit of a plurality of bits in the semiconductor chip, mask dimensions for a feature to determine variations of the feature within each bit; using the processor to predict based on the variations, for each bit of the plurality of bits, a probability of being “0” or “1” to provide predicated probabilities; using the processor to group, based on the predicted probabilities, each bit of the plurality of bits and selecting a subset of bits to provide a subset of predicted results; controlling, using the processor, the chip testing unit to measure each bit of the subset of bits is in a state is “0” or “1” to provide measured results; using the processor to compare the subset of predicted results and the measured results to provide a comparison; and using the processor to determine, based on the comparison, that the semiconductor chip has been fabricated using an altered mask. ### Claim 16 (depends on 15) The computer program product of claim 15, wherein the plurality of bits comprises a static random access memory cell. ### Claim 17 (depends on 15) The computer program product of claim 15, wherein the feature comprises a gate mask dimension. ### Claim 18 (depends on 15) The computer program product of claim 15, wherein the feature comprises a gate dimension over an active area. ### Claim 19 (depends on 15) The computer program product of claim 15, wherein the feature comprises a via dimension. ### Claim 20 (depends on 15) The computer program product of claim 15, wherein the feature comprises a metal feature dimension.