# US 10,769,238 B2 · Matrix multiplication on a systolic array

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- Number: US 10,769,238 B2
- Document ID: US10769238B2
- Status: Granted
- Kind: B2
- Application number: 16/576,144
- Filed: 2019-09-19
- Published: 2020-01-09
- Granted: 2020-09-08
- Earliest claimed: 2017-03-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chia-Yu Chen; Jungwook Choi; Kailash Gopalakrishnan; Victor Han; Vijayalakshmi Srinivasan; Jintao Zhang
- Web page: https://patentgrep.com/patent/US10769238B2

## CPC

- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Techniques facilitating matrix multiplication on a systolic array are provided. A computer-implemented method can comprise populating, by a system operatively coupled to a processor, respective first registers of one or more processing elements of a systolic array structure with respective input data bits of a first data matrix. The one or more processing elements can comprise a first processing element that comprises a first input data bit of the first data matrix and a first activation bit of a second data matrix. The method can also include determining, by the system, at the first processing element, a first partial sum of a third data matrix. Further, the method can include streaming, by the system, the first partial sum of the third data matrix from the first processing element.

## Claims

### Claim 1

A system, comprising:
a memory that stores computer executable components; and
a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise:
a load manager component that populates respective first registers of all processing elements of a systolic array structure with respective input data bits of a first data matrix, wherein the load manager component further inputs a first activation bit of a second data matrix into a first processing element of the processing elements, and the respective input data bits of the first data matrix are maintained in the respective first registers while a matrix multiplication of the first data matrix and the second data matrix is completed.

### Claim 2 (depends on 1)

The system of claim 1, further comprising:
a computation component that determines, during the matrix multiplication, at the first processing element, a first partial sum of a third data matrix based on a first product of the first activation bit and a first input data bit of the first data matrix, and a first initial value of the third data matrix.

### Claim 3

A computer-implemented method, comprising:
populating, by a system operatively coupled to a processor, respective first registers of all processing elements of a systolic array structure with respective input data bits of a first data matrix;
inputting, by the system, a first activation bit of a second data matrix into a first processing element of the processing elements; and
maintaining, by the system, respective input data bits of the first data matrix in the respective first registers while a matrix multiplication of the first data matrix and the second data matrix is completed.

### Claim 4 (depends on 3)

The computer-implemented method of claim 3, further comprising:
determining, by the system during the matrix multiplication, at the first processing element, a first partial sum of a third data matrix based on a first product of the first activation bit and a first input data bit of the first data matrix, and a first initial value of the third data matrix.

### Claim 5 (depends on 4)

The computer-implemented method of claim 4, further comprising:
streaming, by the system during the matrix multiplication, the first partial sum of the third data matrix along a first dimension to a second processing element of the processing elements.

### Claim 6 (depends on 5)

The computer-implemented method of claim 5, further comprising:
determining, by the system during the matrix multiplication, at the second processing element, a second partial sum of the third data matrix based on a second sum of the first partial sum and a second product determined based on a second activation bit of the second data matrix and a second input data bit of the first data matrix stored in the first register of the second processing element.

### Claim 7 (depends on 6)

The computer-implemented method of claim 6, further comprising:
streaming, by the system during the matrix multiplication, the second partial sum of the third data matrix from the second processing element and along the first dimension.

### Claim 8 (depends on 5)

The computer-implemented method of claim 5, further comprising:
determining, by the system during the matrix multiplication, during the matrix multiplication, at the second processing element, a second partial sum of the third data matrix based on a second sum of a second product and a second initial value of the third data matrix, wherein the second product is determined based on the first activation bit and a second input data bit of the first data matrix stored in the first register of the second processing element.

### Claim 9 (depends on 8)

The computer-implemented method of claim 8, further comprising: streaming, by the system during the matrix multiplication, the second partial sum of the third data matrix from the second processing element and along the first dimension.

### Claim 10

A computer program product for facilitating matrix multiplication on a systolic array structure, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing component to cause the processing component to:
populate respective first registers of all processing elements of a systolic array structure with respective input data bits of a first data matrix;
input a first activation bit of a second data matrix into a first processing element of the processing elements; and
maintain respective input data bits of the first data matrix in the respective first registers while a matrix multiplication of the first data matrix and the second data matrix is completed.

### Claim 11 (depends on 10)

The computer program product of claim 10, wherein the program instructions further cause the processing component to:
determine, during the matrix multiplication, at the first processing element, a first partial sum of a third data matrix based on a first product of the first activation bit and a first input data bit of the first data matrix, and a first initial value of the third data matrix.

### Claim 12 (depends on 11)

The computer program product of claim 11, wherein the program instructions further cause the processing component to:
stream, during the matrix multiplication, the first partial sum of the third data matrix along a first dimension to a second processing element of the processing elements.

### Claim 13 (depends on 12)

The computer program product of claim 12, wherein the program instructions further cause the processing component to:
determine, during the matrix multiplication, at the second processing element, a second partial sum of the third data matrix based on a second sum of the first partial sum and a second product determined based on a second activation bit of the second data matrix and a second input data bit of the first data matrix stored in the first register of the second processing element.

### Claim 14 (depends on 13)

The computer program product of claim 13, wherein the program instructions further cause the processing component to:
stream, during the matrix multiplication, the second partial sum of the third data matrix from the second processing element and along the first dimension.

### Claim 15 (depends on 12)

The computer program product of claim 12, wherein the program instructions further cause the processing component to:
determine, during the matrix multiplication, during the matrix multiplication, at the second processing element, a second partial sum of the third data matrix based on a second sum of a second product and a second initial value of the third data matrix, wherein the second product is determined based on the first activation bit and a second input data bit of the first data matrix stored in the first register of the second processing element; and
stream, during the matrix multiplication, the second partial sum of the third data matrix from the second processing element and along the first dimension.