# US 10,769,099 B2 · Devices for time division multiplexing of state machine engine signals > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,769,099 B2 - Document ID: US10769099B2 - Status: Granted - Kind: B2 - Application number: 15/534,994 - Filed: 2015-12-29 - Published: 2017-12-21 - Granted: 2020-09-08 - Earliest claimed: 2014-12-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Harold B Noyes; David R. Brown; Paul Glendenning; Paul D. Dlugosch - Web page: https://patentgrep.com/patent/US10769099B2 ## CPC - G06F 15/7867: {with reconfigurable architecture} - G06F 1/3225: of memory devices - G06F 9/4498: {Finite state machines} - G06F 13/423: {with synchronous protocol} - G06F 15/7857: {using interleaved memory (addressing G06F12/0607)} - G06N 20/00: Machine learning - G05B 19/045: using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) ## Abstract A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line. ## Claims ### Claim 1 A device, comprising: a plurality of blocks, each block of the plurality of blocks comprising a plurality of rows, each row of the plurality of rows comprising a plurality of configurable circuits, and each configurable circuit of the plurality of configurable circuits is directly coupled to a common routing line via a respective output line of a plurality of output lines, wherein the common routing line is an output transmission line shared amongst all configurable circuits of the plurality of configurable circuits, each configurable circuit of the plurality of configurable circuits comprising: an output directly coupled to the respective output line of the plurality of output lines; an automaton comprising a plurality of memory cells, wherein the automaton is configured to analyze at least a portion of a data stream and to output a result of the analysis; and a multiplexer coupled to the automaton and coupled to the output, wherein the multiplexer is configured to transmit the result to the common routing line via the output and; a demultiplexer, wherein the common routing line is configured to transmit the result from each configurable circuit of the plurality of configurable circuits to the demultiplexer, wherein the demultiplexer is configured to selectively transmit individual signals received from the common routing line to an intra-block switch via a row lines selected by the demultiplexer. ### Claim 2 (depends on 1) The device of claim 1, comprising a control system configured to transmit initial programming values to the plurality of blocks. ### Claim 3 (depends on 2) The device of claim 2, wherein the multiplexer is configured to transmit the result based on the initial programming values. ### Claim 4 (depends on 1) The device of claim 1, comprising a control system configured to transmit dynamic programming values to the plurality of blocks during operation of the blocks. ### Claim 5 (depends on 4) The device of claim 4, wherein the multiplexer is configured to transmit the result based on the dynamic programming values. ### Claim 6 (depends on 1) The device of claim 1, comprising the intra-block switch coupled to the demultiplexer. ### Claim 7 (depends on 6) The device of claim 6, wherein the intra-block switch is configured to receive signals related to the result from each configurable circuit of the plurality of configurable circuits from the demultiplexer and route the result from each configurable circuit of the plurality of configurable circuits to a particular row of the plurality of rows. ### Claim 8 (depends on 1) The device of claim 1, wherein each row of the plurality of rows further comprises a local routing matrix comprising the common routing line and coupled to the configurable circuits of that respective row. ### Claim 9 A device, comprising: a state machine lattice comprising: a plurality of blocks, each block of the plurality of blocks comprising: a plurality of rows, each row of the plurality of rows comprising: a plurality of configurable circuits, each configurable circuit of the plurality of configurable circuits comprising a plurality of automatons configured to analyze at least a portion of a data stream and each configurable circuit of the plurality of configurable circuits configured to selectively output a result of the analysis; and a local routing matrix comprising a common routing line directly coupled to at least two configurable circuits of the plurality of configurable circuits via respective output lines of a plurality of output lines and configured to receive the result from each configurable circuit of the at least two configurable circuits of the plurality of configurable circuits, wherein the common routing line is an output transmission line shared amongst the at least two configurable circuits of the plurality of configurable circuits, wherein the local routing matrix comprises a demultiplexer coupled to the common routing line, wherein the demultiplexer is configured to selectively transmit the result from a first configurable circuit of the at least two configurable circuits of the plurality of configurable circuits and selectively transmit the result from a second configurable circuit of the at least two configurable circuits of the plurality of configurable circuits subsequent to transmission of the result from the first configurable circuit of the at least two configurable circuits. ### Claim 10 (depends on 9) The device of claim 9, wherein the local routing matrix comprises a second common routing line directly coupled to at least an additional two configurable circuits of the plurality of configurable circuits. ### Claim 11 (depends on 10) The device of claim 10, wherein the local routing matrix comprises a switching element coupled to the second common routing line. ### Claim 12 A device, comprising: a state machine lattice comprising: a plurality of blocks; an intra-block switch configured to route signals between the plurality of blocks; a row coupled to the intra-block switch, wherein the row comprises: a plurality of configurable circuits, each configurable circuit of the plurality of configurable circuits comprising a plurality of automatons configured to analyze at least a portion of a data stream and each configurable circuit of the plurality of configurable circuits configured to selectively output a result of the analysis; and a local routing matrix comprising a common routing line directly coupled to each of at least two configurable circuits of the plurality of configurable circuits via respective output lines of a plurality of output lines, wherein the local routing matrix is configured to receive the result from each configurable circuit of the at least two configurable circuits of the plurality of configurable circuits, wherein the common routing line is an output transmission line shared amongst the each of the at least two configurable circuits of the plurality of configurable circuits, wherein the local routing matrix comprises a demultiplexer coupled to the common routing line, wherein the common routing line is configured to transmit the result from each configurable circuit of the at least two configurable circuits to the demultiplexer, wherein the demultiplexer is configured to selectively transmit the result from each configurable circuit of the at least two configurable circuits received from the common routing line to the intra-block switch via a row lines selected by the demultiplexer. ### Claim 13 (depends on 12) The device of claim 12, wherein the local routing matrix comprises a second common routing line directly coupled to at least an additional two configurable circuits of the plurality of configurable circuits and configured to receive the result from each configurable circuit of at least the additional two configurable circuits of the plurality of configurable circuits. ### Claim 14 (depends on 13) The device of claim 13, comprising a switching element coupled to the second common routing line and the intra-block switch. ### Claim 15 (depends on 12) The device of claim 12, comprising a second common routing line configured to transmit a signal to at least the two configurable circuits of the plurality of configurable circuits. ### Claim 16 (depends on 15) The device of claim 15, comprising a switching element coupled to the second common routing line and the intra-block switch. ### Claim 17 (depends on 16) The device of claim 16, wherein the switching element comprises a multiplexer. ### Claim 18 A device, comprising: a state machine lattice comprising: a row, comprising a plurality of configurable circuits, each configurable circuit of the plurality of configurable circuits comprising a plurality of automatons configured to analyze at least a portion of a data stream and each configurable circuit of the plurality of configurable circuits configured to selectively output a result of the analysis; a plurality of row routing lines, wherein each row routing line is configured to be directly coupled to one or more configurable circuits of the plurality of configurable circuits via a respective output line of a plurality of output lines, wherein each row routing line is configured to transmit the result from each configurable circuit of the one or more configurable circuits directly coupled thereto; and an intra-block switch, wherein the intra-block switch comprises a multiplexer coupled to at least two row routing lines of the plurality of row routing lines, wherein the multiplexer is configured to selectively drive-out the result from each row routing line of the at least two row routing lines of the plurality of row routing lines to a common block routing line as a shared output transmission line. ### Claim 19 (depends on 18) The device of claim 18, wherein a state machine comprises a second row and a second intra-block switch coupled to the second row. ### Claim 20 (depends on 19) The device of claim 19, wherein the intra-block switch comprises the shared block routing line coupled to the multiplexer and the second intra-block switch, wherein the multiplexer is configured to selectively route the result from a first row routing line of the at least two row routing lines to the second row via the shared block routing line and the second intra-block switch. ### Claim 21 (depends on 18) The device of claim 18, wherein the intra-block switch comprises a second block routing line and a second multiplexer, wherein the intra-block switch is configured to transmit a signal received along the second block routing line to the row via the second multiplexer. ### Claim 22 A device, comprising: a state machine lattice, comprising: an input configured to receive a data stream; an inter-block switch circuit coupled to the input and to a block, wherein the inter-block switch circuit is configured to transmit to the block a time division multiplexed data signal that is generated based upon the data stream, wherein the block comprises: a demultiplexer configured to generate a demultiplexed data signal based upon the time division multiplexed signal; a storage element configured to receive and store the demultiplexed data signal; and a configurable circuit comprising a plurality of automatons configured to receive the demultiplexed data signal from the storage element and analyze at least a portion of the demultiplexed data signal, wherein the configurable circuit is configured to selectively output a result of the analysis. ### Claim 23 (depends on 22) The device of claim 22, comprising a multiplexer between the inter-block switch circuit and input. ### Claim 24 (depends on 22) The device as claimed in claim 22, wherein the inter-block switch circuit includes a multiplexer configured to generate the time division multiplexed data signal.